Abstract: Provided is a wafer polishing device including: a table configured to mount a wafer and to rotate the wafer; and a polisher spaced apart from a first surface of the wafer and configured to polish the first surface of the wafer by spraying a fluid toward the first surface of the wafer, wherein a length of the polisher is greater than a radius of the wafer.

Abstract: A processor-implemented method includes randomly generating a plurality of orderings of tasks for a plurality of tasks of a training dataset, determining, based on training a first base model using the training dataset according to each of the plurality of orderings of tasks, an evaluation information set of the first base model trained according to each of the plurality of orderings of tasks, and determining, based on the evaluation information set of the first base model trained according to each of the orderings of tasks, a piece of first target evaluation information of the first base model corresponding to the training dataset.

Abstract: Disclosed is a convolutional neural network (CNN) processing apparatus and method, the method including acquiring kernel information indicating a skip target of a convolution operation; determining which convolution operations, between at least one input element of an input and respective kernel elements of kernel elements of a convolutional layer, to skip based on the kernel information; and implementing the convolutional layer by skipping respective convolution operations, of the convolutional layer, based on a result of the determining, and otherwise performing remaining convolution operations of the convolutional layer.

Abstract: A processor-implemented method including generating a text query based on an image query by inputting the image query to a trained first model, obtaining, from a database, one or more images as a first retrieval result for the image query and one or more texts as a second retrieval result for the text query, generating a multimodal score for a candidate image set by inputting, to a trained second model, the image query, the text query, and the candidate image set determined based on the first retrieval result and the second retrieval result, and determining one or more target images from the candidate image set based on the multimodal score for the candidate image set.

Abstract: A method of manufacturing a semiconductor device may include: loading a substrate onto a substrate holder disposed in a process chamber; forming a first material layer on a surface of the substrate by supplying a first reaction gas into the process chamber using a first gas supply unit; discharging a first exhaust gas including an excess of the first reaction gas from the process chamber; forming a second material layer on the surface of the substrate by supplying a second reaction gas into the process chamber using a second gas supply unit; discharging a second exhaust gas including an excess of the second reaction gas from the process chamber; introducing the first exhaust gas into a scrubber and treating the first exhaust gas in the scrubber; and introducing the second exhaust gas into a diversion line and treating the second exhaust gas.

Abstract: A clothes care apparatus including a cabinet; a treatment compartment to be inside the cabinet to accommodate clothes; and a machine room to be at one side of the treatment compartment. The machine room includes: a heat exchanger to dehumidify and heat air in the treatment compartment; a steam generator to generate steam to be sprayed into the treatment compartment; a water collection duct to store water condensate occurring during the air being dehumidified and heated; and a water supply and drain unit to be selectively controlled to supply water from an external water supply source to the steam generator or to be selectively controlled to discharge the condensate water stored in the water collection duct to an external space of the clothes care apparatus.

Abstract: A computing device includes a memory configured to store input data and a plurality of instructions, a processor configured to execute instructions of a predetermined length among the plurality of instructions received from the memory, a command queue configured to receive, from the processor, instructions corresponding to an accelerator among the instructions of the predetermined length and generate a merged instruction by merging the received instructions through an arithmetic logic unit (ALU), and the accelerator configured to perform an operation between the input data and pre-stored data in response to receiving the merged instruction from the command queue.

Abstract: A display device including a mirror display including a black layer with adjustable transmittance, a transparent display layer, arrangeable on the front surface of the black layer so as to display an image, and a mirror layer, arrangeable on the front surface of the transparent display layer, with adjustable reflectivity; and one or more processors to adjust the transmittance of the black layer and the reflectively of the mirror layer according to a current operation state of the display device from among a plurality of operation states of the display device, and controlling whether to display an image on the transparent display layer.

Abstract: Provided are an electronic apparatus and a method for controlling the electronic apparatus. The electronic apparatus includes: a communicator; a display; a memory storing at least one instruction; and a processor configured to execute the at least one instruction. The processor is configured to: identify a registration request and context information based on at least one signal received from a target device through the communicator; based on the registration request and a strength of the at least one signal indicating the context information, control the display to provide a user interface for registering the target device; and based on a user input to add the target device as a device constituting an Internet of Things (IoT) network being received through the user interface, register the target device as the device constituting the IoT network.

Abstract: According to an aspect of the present disclosure, a memory device includes a first buffer configured to store input temperature data for a memory cell as first temperature data based on a clock signal, and to output the first temperature data, a second buffer configured to receive and to store the first temperature data from the first buffer based on the clock signal, and to output the first temperature data as second temperature data, a delay circuit configured to output a delayed clock signal generated by delaying the clock signal, a third buffer configured to output inputted third temperature data as output temperature data based on the delayed clock signal, and a filter circuit configured to remove noise from the input temperature data based on the first temperature data, the second temperature data, and the third temperature data.

Abstract: An electronic device according to an embodiment of the disclosure may include a seating part, and a transmitting part protruding from the seating part. The transmitting part may include a transmitting part housing that forms the exterior of the transmitting part, and a transmitting coil disposed inside the transmitting part housing and used to transmit power to an external electronic device. The transmitting part housing may include a first region in which the transmitting coil is disposed and which extends with a first radius of curvature, and a second region which extends from the first region with a second radius of curvature that is smaller than the first radius of curvature.

Abstract: A processor-implemented method including generating first topology data from raw data through a first model configured to segment a pattern corresponding to a semiconductor fabrication process, generating second topology data in which the first topology data is refined through a second model configured to remove a defect included in the pattern, and calculating reliability data corresponding to the semiconductor fabrication process by matching the first topology data to the second topology data.

Abstract: A foldable electronic device includes a first housing, a second housing, a hinge structure coupled to the first housing and the second housing, a hinge housing where the hinge structure is disposed, a first dustproof structure and a second dustproof structure disposed between the first housing and the hinge housing, and a first support structure disposed between the first dustproof structure and the second dustproof structure in a lengthwise direction of the hinge housing. The first dustproof structure and the first support structure make contact with each other or are spaced apart from each other by a distance smaller than a length of the first support structure, and the second dustproof structure and the first support structure make contact with each other or are spaced apart from each other by a distance smaller than the length of the first support structure.

Abstract: An image processing device includes a multimedia Intellectual Property configured to process image data and generate source data, and a frame buffer compressor configured to compress the source data, generate compressed data, decompress the compressed data and generate output data. The frame buffer compressor configured to generate quantized data by performing quantization on the source data using a plurality of pixel position offsets corresponding to each of coordinates of a plurality of image pixels included in the source data, and a quantization coefficient, and generate the compressed data by processing the quantized data.

Abstract: An image decoding method may include obtaining information regarding adaptive loop filtering from a bitstream, obtaining a first filtered residual sample corresponding to a current sample by performing filtering based on a residual sample for the current sample and a first filter, obtaining a second filtered residual sample corresponding to the current sample by performing filtering based on the first filtered residual block and a second filter, and obtaining an adaptive loop filtered sample based on the first filtered residual sample, the second filtered residual sample, and at least one adaptive filter coefficient obtained from the information regarding the adaptive loop filtering.

Abstract: An integrated circuit device includes a plurality of first source/drain areas, a plurality of second source/drain areas spaced apart from the plurality of first source/drain areas in a first direction and stacked above the plurality of first source/drain areas in the first direction, a first contact disposed on a lower surface of each of the plurality of first source/drain areas in the first direction, a second contact disposed on an upper surface of each of the plurality of second source/drain areas in the first direction, a conductive rail electrically connected to the first contact or the second contact and extending in the first direction, a first diffusion breaker disposed beside the conductive rail in a second direction intersecting the first direction, and a second diffusion breaker spaced apart from the first diffusion breaker in the second direction with the conductive rail in between.

Abstract: A semiconductor device includes a substrate, a gate pattern, and a conductive line pattern. The substrate has a first surface and a second surface and includes an isolation pattern that defines plural pixel regions, and a photoelectric conversion region in each pixel region and a transistor for each of the pixel regions. The gate pattern of the transistor is disposed on the first surface of the substrate. The conductive line pattern is disposed on the first surface of the substrate and vertically overlaps the isolation pattern in plan view. A top surface of the conductive line pattern is located at the same level as a top surface of the gate pattern, a width of the conductive line pattern is less than a width of the isolation pattern, and the isolation pattern comprises a conducive isolation pattern and a dielectric isolation pattern.

Abstract: A lower structure of a semiconductor device includes a semiconductor substrate including a chip region, and an edge region of at least one side of the chip region; an interconnection structure disposed on the semiconductor substrate, and including a plurality of interconnection pattern layers and an insulating layer covering the plurality of interconnection pattern layers; a first insulating structure on the interconnection structure; a lower conductive pattern on the first insulating structure; and a second insulating structure on the lower conductive pattern. An upper structure is on the lower structure and includes an upper conductive pattern on the second insulating structure. The first insulating structure includes a first insulating portion and a second insulating portion. At least a portion of a side surface of the lower structure is defined by the second side of the second insulating portion.

Abstract: A semiconductor package may include a package substrate having upper and lower surfaces opposing each other, a control chip and a chip stack structure disposed on the upper surface of the package substrate, a first pad and a first pattern disposed on the lower surface of the package substrate and horizontally spaced apart from each other, and a dummy pattern disposed on the lower surface of the package substrate and interposed between the first pad and the first pattern, in which the dummy pattern is spaced apart from the first pad and the first pattern.

Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.