Abstract: A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

Abstract: A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar register and a second data in a vector register. Upon fetching the first data as a first operand and the second data as a second operand, the processing unit performs an operation between the first and second operands in response to an operator. After operations, the result is subsequently stored in a second scalar register.

Abstract: A method and a device including, in one embodiment, a multiply array and at least one adder to perform a floating-point multiplication followed by an addition when operands are in floating-point format. The device is also configured to perform an integer multiplication followed by an accumulation when operands are in integer format. The device is further configured to perform a floating-point multiply-add or an integer multiply-accumulation in response to control signals. In another embodiment, the device contains an adder and the adder is capable of performing a floating-point addition and an integer accumulation. The adder is configured to be extra wide to reduce operand misalignment. Moreover, the device stalls the process in response to operand misalignment.

Abstract: A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data read into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

Abstract: A method and a device for maintaining logic state stored in a storage device are described. For one embodiment, the device precharges at least two complimentary nodes in a storage device during the precharge cycle. During the evaluation cycle, the device receives an input data. After receipt of the input data, device stores at least one logic state at a storage node according to the input data. The device includes at least one conducting path to limit one store per each evaluation stage.

Abstract: A dual access debugging architecture. This architecture allows the microprocessor to select between external debugging, supported via the physical system interface, and internal debugging, supported via logic within the microprocessor which is controlled by decoded software instructions. In one example of the present invention, a microprocessor includes a system bus interface and a program decoder which is coupled to the system bus interface. The system bus interface is coupled to a system bus to which external memory is coupled. Debugging operations are stored as debugging instructions in the external memory. When these debugging instructions are retrieved from memory, through the system bus and the system bus interface, they are decoded in the program decoder of the microprocessor and they in turn cause the microprocessor to enter a first debugging mode which is controlled by the debugging instructions. The first debugging mode may be referred to as an internal programmable method.

Abstract: A PLL is implemented as a full differential circuit to improve the jitter performance and the operating voltage range. A process-compensated common-mode feedback is designed in the differential charge pump which together with loop filter of MOSFET capacitors maximizes the dynamic voltage range. A high-frequency divider capable of divide-mode change-on-flight is developed with eight divide mode programmability. A PLL start-up control circuit makes the PLL start and work under difficult conditions.

Abstract: A memory array structure includes a first word line connected to a single port memory cell and a dual port memory cell. The memory array structure also includes a second word line connected to the dual port memory cell. The second word line can control the data storage of the dual port memory during the second phase of a clock signal.

Abstract: A reduced line select decoder for a memory array provided comprising a plurality of memory cells arranged at least in one column, a bit line pair connected to the memory cells arranged in one column, a sense amplifier coupled to a bit line pair for differentially amplifying the voltages on the bit line pair in accordance with the voltage on the sense drive line, and a sense amplifier control input responsive to activation of a sense instructing signal to latch data into the sense amplifier and a pair of read/write control signals to select and provide a read/write operation to a selected bit line and connecting to write buffer.

Abstract: One embodiment of the present invention provides a state machine that receives as input a clock signal and determines a frequency relationship between circuits. The state machine generates outputs that control buffer circuits. The buffer circuits latch signals input to them until the output signals from the state machine cause the buffer circuits to latch new input signals. The buffer circuits are used to latch data until that data can be used appropriately.

Abstract: A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.

Abstract: A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction within a computer system. In one embodiment, a processing unit comprises a bus arbitrator having bus control lines for controlling a bus, which transmits address and data information. The arbitrator is capable of issuing multiple consecutive read or write requests including at least one read request on the bus without releasing control by the processing unit over the bus during the consecutive read or write requests. In addition, the arbitrator is also designed to abort consecutive read requests during address cycles in response to bus control lines.

Abstract: A memory device including a first set of memory cells, a second set of memory cells having preprogrammed states, and a circuit configured to access data included in a first segment of memory cells. When data is read from the second set of memory cells the circuit includes an enable signal to determine whether the data outputted by the second set of memory cells is preprogrammed data or data stored during normal operation. For one embodiment, data written into or retrieved from the memory cells is performed in a consistent fashion between the first set of memory cells and the second set of memory cells.

Abstract: A writeback cache cell and method for operating a writeback cache. In one example, the method includes reading a memory cell of the writeback cache through a first port to determine whether the memory cell stores a first value which indicates that a memory location in the writeback cache has updated data relative to data stored in another memory and writing the first value to the memory cell through a second port if the reading step determined that the memory cell did not store the first value. An example of a writeback cache cell includes a memory cell storing a first value which indicates that a memory location in the writeback cache has updated data relative to data stored in another memory location when the data stored in the another memory location is invalid and includes a first port coupled to the memory cell and a second port coupled to the memory cell.

Abstract: A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.