Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.

Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.

Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first conductivity type semiconductor layer in the plurality of openings, forming a second conductivity type semiconductor layer over the first conductivity type semiconductor layer in the plurality of openings, and selectively etching the second conductivity type semiconductor layer using an upper surface of the first conductivity type semiconductor layer as a stop to form a recess in the plurality of openings.

Abstract: The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.

Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.

Abstract: A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell.

Abstract: Methods of forming a microelectronic structure are provided, the microelectronic structure including a first conductor, a discontinuous film of metal nanoparticles disposed on a surface above the first conductor, a carbon nano-film formed atop the surface and the discontinuous film of metal nanoparticles, and a second conductor disposed above the carbon nano-film. Numerous additional aspects are provided.

Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay.

Abstract: The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.

Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.

Abstract: A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.

Abstract: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.

Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.

Abstract: A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments, multiple memory levels are formed stacked above a single substrate.

Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.