Abstract: A file synchronization system that includes a non-volatile memory for storing at least one bookmark respective to a file; a telecommunication mechanism for receiving a new bookmark value respective to this file; and a controller operative to update the respective bookmark according to the new bookmark value; and to control presentation of the file in accordance with the updated bookmark value. A plurality of bookmarks that associate to a single file are stored in the file synchronization system, each such bookmark respective to a different user.

Abstract: A method of executing an erasing instruction to erase host data from a flash memory device is provided. The method initiates with receiving from a host device an erase instruction to erase host data from an array of NAND flash memory cells grouped into separately-erasable device blocks, each device block including multiple device pages, the host data being a portion of device data that is stored in a device block. The host data is marked as erased, and a message is sent to the host device indicating that the host data has been erased.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: Techniques are presented that allow a memory card operable according to two protocols (such as a legacy protocol and newer protocol), and having a corresponding dual interface, to be used with hosts that support the new protocol as well as having backward compatibility with legacy hosts, while preventing the use of legacy cards with hosts that support the new protocol but do not support the legacy protocol. The card that supports the new protocol has a similar form factor to the legacy card, includes an indentation. A host that supports the new, but not the legacy, type card includes a mechanical structure within the attachment slot that, based on the card indentation, can distinguish the card types and prevent the non-supported card from being attached.

Abstract: A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.

Abstract: Techniques are presented that allow a memory card operable according to two protocols (such as a legacy protocol and newer protocol), and having a corresponding dual interface, to be used with hosts that support the new protocol as well as having backward compatibility with legacy hosts, while preventing the use of legacy cards with hosts that support the new protocol but do not support the legacy protocol. The card that supports the new protocol has a similar form factor to the legacy card, includes an indentation. A host that supports the new, but not the legacy, type card includes a mechanical structure within the attachment slot that, based on the card indentation, can distinguish the card types and prevent the non-supported card from being attached.

Abstract: A storage device with a memory, a controller, and a host interface, and a method of handling commands in a storage device are provided to execute commands in a storage device having a write-once read-many device configuration, transparently to a host device. The memory containing a database having entries each entry for a logical memory address and containing information for converting that logical memory address to a redirected logical memory address that represents a memory location where data associated with that logical memory address actually resides. The controller performs, when the host interface is operatively coupled to a host device, to receive a command specifying a logical memory address and interpret the command based on information extracted from the database. The controller executes the command according to the information, transparently to the host device.

Abstract: The present invention is related with the management of memory in environments of limited resources, such as those found for example in a smart card. In a more particular manner, the invention relates to a method of managing the data storage resources of volatile memory, the object of which is to reduce the size of volatile memory necessary to implement the stack of the system, and thereby to reserve more volatile memory available for other needs or procedures of the system or of other applications When the stack grows and comes close to its established limit, the system carries out a transfer of a stack block located in the volatile memory to an area of non-volatile memory, hence this transfer allows a compression of the stack increasing its size in a virtual manner.

Abstract: A storage device has two connectors for transferring data files: a first connector through which data files can be transferred at an accelerated speed, and a second connector through which data files can be transferred at a conventional speed. According to the present disclosure a user can select the speed (i.e., “normal speed” or “accelerated speed”) at which s/he wants to transfer a data file from a host to the storage device, and vice versa, by connecting the host to the proper connector of the storage device. The first connector is internally connected to a plurality of controllers that facilitate data transfers at the accelerated speed, and the second connector is internally connected to a controller that facilitates data transfers at the normal speed.

Abstract: A memory card structure includes a memory card body dimensioned to house a memory and a controller, and the memory card body has an edge connector portion having a thickness that complies with a memory card specification. The memory card body includes a recessed portion dimensioned to receive an external plug. The memory card structure also includes an electrical connector that is coupleable to a Universal Serial Bus (USB) plug and that is electrically coupled to at least one of the memory and the controller. The electrical connector extends from the recessed portion of the memory card body.

Abstract: A method executed by a circuit for counting electrons in storage cells in an array of at least two storage cells is provided. The method includes providing a storage array of at least two storage cells, and each of said at least two storage cells containing an unknown amount of electrons. A receiving array of at least two receiving cells is provided, where said at least two receiving cells initially contain no electrons. Then, extracting a layer of said electrons from said storage array of cells and inserting said layer into corresponding locations in said receiving array. The method then repeats said steps of extracting and inserting while at least one of said at least two storage cells is not empty. The method counts, for each said storage cell in said storage array, a productive-extraction amount.

Abstract: A data storage area of a data storage device is partitioned logically between a user storage area and a device storage area. Source data stored securely in the device storage area is copied as derivative data to the user storage area, or is used as a basis for creating derivative data stored in the user storage area, whenever the data storage device is initialized. In one embodiment, the data storage area is read-write and the device storage area has embodied thereon device system code, executed by a controller of the data storage device, for writing source data to the device storage area only if the source data satisfies a predetermined condition. Examples of derivative data include an autorun file, a volume label and user identification. Data from a host may be stored reversibly in the user storage area but must be stored securely in the device storage area.

Abstract: A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably connectable to a cache memory. The processor is adapted, subsequent to an initial interrogation of the cache interface, to determine whether the cache memory is connected to the cache interface by inspecting an indication of the presence or the absence of the cache memory, the indication being stored in a register in the processor or in a memory associated with the processor such that the inspecting avoids repeat interrogation of the cache interface, to communicate with the cache memory and the hard disk drive such that the processor has access to the cache memory when the cache memory is connected to the cache interface, and to communicate with the hard disk drive when the cache memory is disconnected from the cache interface.

Abstract: A portable media device 100 including two onboard hardware media decoders (124, 128) operative to decode a given digital content item 148 is provided. In some embodiments, one of the onboard hardware media decoders 128 has a relatively high power consumption and produces a relatively ‘high quality’ media signal, and the other of the onboard hardware media decoder 124 has a relatively low power consumption and produces a relatively ‘low quality’ media signal.

Abstract: A non-volatile storage device with built-in ruggedized features is disclosed. The device processes a write command to a logical block address by writing the data from the command to a non-volatile memory within the non-volatile storage device and conditionally associating the data received from the command with its corresponding logical block address. Two or more received write commands define a set of commands associated with an atomic transaction. When an end of set command is received, the device unconditionally associates the received data with each write command with its corresponding logical block address. If a power loss interrupts the reception of a set of commands, the non-volatile storage device may recover the last consistent data state before the atomic transaction was started. A write command transaction identifier allows the device to associate the command with a thread of commands that define an atomic transaction in a multithreaded system.

Abstract: A method for protecting information in a device includes providing a device with a non-secure hardware domain, a processor having a software-controlled mode of operation, and a secure hardware domain having a secure memory that is inaccessible by the processor when the processor is operating in the software-controlled mode of operation. Data from the non-secure hardware domain is established in the secure hardware domain. Computing operations are executed on the data in the secure hardware domain to produce a result. The secure hardware domain is purged, while retaining the result therein. The result is thereafter returned from the secure hardware domain into the non-secure hardware domain.

Abstract: A method and system for organizing groups of data in a storage device having a non-volatile memory consisting of higher performance or endurance portion and a lower performance or endurance portion are disclosed. The method may include steps of determining a data usage status for a group of data in only one of the two portions, and if a data usage criterion is met, moving the group of data to the other of the two portions of the non-volatile memory. In another implementation, the method may include determining a data usage status of groups of data in both portions of the non-volatile memory and moving a group of data from one portion to the other if an appropriate data usage criterion is met so that groups of data may be maintained in a portion of the non-volatile memory most suited to their usage patterns.

Abstract: Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divisor having a second number of terms is also received. During at least one stage of a multi-stage polynomial division operation using the portion of the codeword and the divisor, the portion of the received codeword to be divided by the divisor is adjusted based on a result of a comparison of the first number to the second number.

Abstract: A recording unit includes one or more signal sensors and a recording controller. The recording controller is configured to execute a first recording instruction to record first data received from the one or more signal sensors. The first data is recorded according to first recording rules that specify a first value of a parameter. The recording controller is also configured to, in response to an irregularity detected in the first data, execute a second recording instruction to record second data received from the one or more signal sensors. The second data is recorded according to second recording rules that specify a second value of the parameter, where the second value differs from the first value.

Abstract: Programmer's data is initially stored in a memory device of the storage device by using an MBC storage scheme. After the storage device is embedded in a host device, the programmer's data is internally read from the memory device by using conventional read reference voltages, and the number of erroneous data bits in the programmer's data is calculated. If the programmer's data includes an uncorrectable number of erroneous data bits, the programmer's data is iteratively reread by using unconventional read reference voltages with decreased levels. The iteration process, which includes decreasing the level of the read reference voltages and recalculating the number of erroneous data bits, is terminated when the number of erroneous data bits in the programmer's is less than or equals a predetermined number of erroneous data bits, after which the storage device restores the programmer's data and conventionally rewrites it into the memory device.