Patents Assigned to Sanera Systems Inc.
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Patent number: 7194550Abstract: A unified networking device communicates directly with storage devices and servers in the data center and communicates directly with switches and routers outside of the data center environment. The unified networking device manages data transfers between storage devices, between a storage device and a server, between a storage device and a web switch, and between a storage device and a router. The unified networking device is configured to perform data transfers while bypassing a server. The unified networking device is further configured to perform multi-protocol conversion.Type: GrantFiled: August 30, 2001Date of Patent: March 20, 2007Assignee: Sanera Systems, Inc.Inventors: Joseph I. Chamdani, Raj Cherabuddi, Sudhakar Muddu
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Patent number: 7110394Abstract: A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.Type: GrantFiled: June 25, 2001Date of Patent: September 19, 2006Assignee: Sanera Systems, Inc.Inventors: Joseph I. Chamdani, Michael Corwin, Matthew Rogge
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Patent number: 7088735Abstract: Processing a data packet in a multiple protocol system area network is disclosed. A paddle card comprising a first paddle card that supports a first communication protocol or a second paddle card that supports a second communication protocol is received. The communication protocol supported by the received paddle card is identified. Data packets from the received paddle card are processed according to the identified communication protocol.Type: GrantFiled: February 5, 2002Date of Patent: August 8, 2006Assignee: Sanera Systems, Inc.Inventors: Richard D. Reohr, Jr., Joseph E. Pelissier, Joseph I. Chamdani
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Patent number: 6985975Abstract: A device for ensuring reliable data packet throughput in a redundant system includes a splitter that creates copies of a data packet and sends each copy to a separate intermediate source for processing, parallel buffers for receiving the processed packets from the intermediate sources, and a comparator for determining whether the data packets are equivalent.Type: GrantFiled: June 29, 2001Date of Patent: January 10, 2006Assignee: Sanera Systems, Inc.Inventors: Joseph I. Chamdani, Michael Corwin
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Patent number: 6968491Abstract: Generating a check matrix includes defining a set of column vectors. A matrix operable to have a plurality of entries is initiated. Each entry has a submatrix that includes a function of a subset of the set of column vectors. The following is repeated until a last entry of the matrix is reached. Subsets of the set of column vectors are generated from the set of column vectors, and an entry is generated from each subset. A weight associated with each entry is calculated, and an entry having a minimum weight is selected. The selected entry is added to the matrix, and the subset of column vectors associated with the selected entry is removed from the set of column vectors. The matrix is reported.Type: GrantFiled: April 8, 2002Date of Patent: November 22, 2005Assignee: Sanera Systems Inc.Inventors: Liuxi Yang, Yu Fang, Ulrich Stern, Joseph I. Chamdani
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Patent number: 6920601Abstract: Generating a check matrix includes defining a generator function operable to yield check bits associated with a word. A set of primitive elements is calculated from the generator function. A set of check matrix columns is generated, where each check matrix column includes a matrix having a subset of the set of primitive elements. A check matrix is generated from a subset of the set of check matrix columns, where the check matrix yields a syndrome that comprises an error pattern for the word. The check matrix is reported.Type: GrantFiled: April 8, 2002Date of Patent: July 19, 2005Assignee: Sanera Systems Inc.Inventors: Ulrich Stern, Joseph I. Chamdani, Yu Fang, Liuxi Yang
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Patent number: 6920588Abstract: Transmitting data includes receiving a serial sequence of code words. Each code word includes a word and check bits, where the word includes a sequence of word symbols, and the check bits includes a sequence of check bit symbols. The following is repeated until a last word symbol of a last code word is reached: selecting a next code word, and inserting a next word symbol of the selected code word into a vector. The following is repeated until a last check bit symbol of the last code word is reached: selecting a next code word, and inserting a next check bit symbol of the selected code word into the vector. The vector is transmitted.Type: GrantFiled: April 8, 2002Date of Patent: July 19, 2005Assignee: Sanera Systems Inc.Inventors: Liuxi Yang, Yu Fang, Ulrich Stern, Joseph I. Chamdani