Abstract: A data packet switch, in general, and an Asynchronous Transfer Mode switch, in particular employing a plurality of physically separate memory modules operates like a single shared memory switch by allowing sharing of all of the memory modules among all of the inputs and outputs of the switch. The disclosed switching apparatus consists of multiple independent stages where different stages of the switch operate without a common centralized controller. The disclosed switch removes performance bottleneck commonly caused by use of a centralized controller in the switching system. Incoming data packets are assigned routing parameters by a parameter assignment circuit based on packets' output destination and current state of the switching system. The routing parameters are then attached as an additional tag to input packets for their propagation through various stages of the switching apparatus.