Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

Abstract: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.