Patents Assigned to Sanyo Electric Co., Ltd., a Japan Corporation
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Publication number: 20040161935Abstract: This method provide a method for fabricating a semiconductor device in which waste water generated by a step of processing a semiconductor is filtered to be clean. In the method, removables 12 trapped by a first filter film 10 are used as a second filter film 13, and clogging of the first filter film 10 is prevented, and an external force such as bubbles is applied to the second filter film 13 to maintain filtering capacity. And when removables are mixed with the filtered water, the filtered water is recirculated again to the tank in which the waste water is stored, and after it is checked that a desired inclusion rate has been reached filtration is started again.Type: ApplicationFiled: February 18, 2004Publication date: August 19, 2004Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Motoyuki Tsuihiji, Hirofumi Iinuma
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Publication number: 20040154742Abstract: The present invention solves a problem that in a wire bonding process, an inert gas used for prevention of oxidation of a substrate gave rise to shimmer due to the temperature difference during bonding, thereby degrading the precision of pattern recognition. With this invention's bonding device 21 provided with recognition device, a shimmer prevention blow mechanism 31 is disposed between a ring illumination 25 and a working hole 24 and near working hole 24. Though the nitrogen gas that blows out from working hole 24 gives rise to shimmer due to temperature difference, this shimmer can be blown away by the nitrogen gas blow from shimmer prevention blow mechanism 31. As a result, the recognition precision of a recognition camera can be improved and the wire bonding precision of the &mgr;m order can be improved.Type: ApplicationFiled: February 3, 2004Publication date: August 12, 2004Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Kouji Seki, Noriyasu Sakai, Toshihiko Higashino
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Publication number: 20040155089Abstract: The present invention solves a problem that in a wire bonding process, an inert gas used for prevention of oxidation of a substrate gave rise to shimmer due to the temperature difference during bonding, thereby degrading the precision of pattern recognition. With this invention's bonding device 21, shielding lids 31, 32, and 33 are disposed at upper and lower parts of a ring illumination 25 and at a lower part of lens barrel 29. Shimmer 37 of nitrogen gas that blows out from a working hole 24 can thus be prevented from entering inside ring illumination 25, especially by shielding lid 31 at the lower part of ring illumination 25. As a result, the recognition precision of a recognition camera can be improved and the wire bonding precision of the &mgr;m order can be improved.Type: ApplicationFiled: February 2, 2004Publication date: August 12, 2004Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Kouji Seki, Noriyasu Sakai, Toshihiko Higashino
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Publication number: 20030170922Abstract: A light irradiating device (68) having the good radiation characteristic comprises a plurality of conductive paths (51) that are electrically separated, a photo semiconductor chips (65) fixed onto desired conductive path (51), and a resin (67) for covering the photo semiconductor chips (65) to support the conductive paths (51) integrally.Type: ApplicationFiled: March 12, 2003Publication date: September 11, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Kouji Takahashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa
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Publication number: 20030062587Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: ApplicationFiled: November 7, 2002Publication date: April 3, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Publication number: 20030058030Abstract: Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2Vdd.Type: ApplicationFiled: October 2, 2002Publication date: March 27, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventor: Takao Myono
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Publication number: 20030011058Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: ApplicationFiled: September 9, 2002Publication date: January 16, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Publication number: 20020106860Abstract: To increase the withstand voltage and reduce ON-state resistance, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that the LP layer is formed up to the side of the drain region through an active region under the gate electrode and an SLN layer is formed from the drain region to a part before the active region.Type: ApplicationFiled: January 4, 2002Publication date: August 8, 2002Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Eiji Nishibe, Shuichi Kikuchi, Takao Maruyama
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Publication number: 20020041005Abstract: To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad• polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.Type: ApplicationFiled: August 7, 2001Publication date: April 11, 2002Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Nobuyuki Sekikawa, Koichi Hirata, Wataru Andoh, Noriyasu Katagiri
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Publication number: 20010029093Abstract: When an element isolation film is formed by the LOCOS technique, as-an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: ApplicationFiled: February 15, 2001Publication date: October 11, 2001Applicant: Sanyo Electric Co., Ltd., a Japan CorporationInventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
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Publication number: 20010025987Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N−layer 22A) and deep in the vicinity of the drain region 5 (second N−layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.Type: ApplicationFiled: May 10, 2001Publication date: October 4, 2001Applicant: Sanyo Electric Co., Ltd., a Japan CorporationInventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi