Patents Assigned to Sanyo Electric Co., Ltd., a Osaka Japan Corporation
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Publication number: 20050056898Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.Type: ApplicationFiled: October 20, 2004Publication date: March 17, 2005Applicant: Sanyo Electric Co., Ltd., a Osaka Japan CorporationInventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
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Publication number: 20040256711Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: ApplicationFiled: August 29, 2003Publication date: December 23, 2004Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan CorporationInventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Publication number: 20040198050Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Since a conductive plated layer 4 is formed after through holes 21 are formed in the insulation resin 2 by using an insulation resin sheet 1 overcoated on a single side of the conductive layer 3 with insulation resin 2, a multi-layer connection structure can be achieved by the second conductive path layer 6 which is connected, in multi layers, to the first conductive path layer 5 formed by etching the conductive plated layer 4.Type: ApplicationFiled: April 14, 2004Publication date: October 7, 2004Applicant: Sanyo Electric Co., Ltd., an Osaka Japan CorporationInventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
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Publication number: 20040178459Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.Type: ApplicationFiled: March 25, 2004Publication date: September 16, 2004Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan corporationInventors: Eiji Nishibe, Shuichi Kikuchi
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Publication number: 20040070074Abstract: The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devices 30A, 31A, 32, 33A, 34A and 38. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire.Type: ApplicationFiled: July 18, 2003Publication date: April 15, 2004Applicant: Sanyo Electric Co., Ltd., an Osaka, Japan corporationInventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Noriyasu Sakai, Hitoshi Takagishi, Kouji Takahashi, Kazuhisa Kusano
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Publication number: 20040051125Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.Type: ApplicationFiled: August 29, 2003Publication date: March 18, 2004Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan corporationInventors: Shuichi Kikuchi, Eiji Nishibe