Abstract: A packet network interface apparatus includes a media access control (MAC) module for constructing a packet for transmission over a packet network and a physical coding sublayer (PCS) module for encoding the packet for transmission over a physical interface. An inter packet gap module located between the MAC module and the PCS module directly transfers data to the PCS module while maintaining a certain inter packet gap by deleting or inserting idle characters. The inter packet gap module has at least one memory module for temporary storage of packet data. The modules preferably operate in a common time domain.

Abstract: A CRC (Cyclic Redundancy Check) code for a data message is created by placing an initial portion of the data message on a bus of width W bits consisting of an integral number N of segments of width S such that the initial portion of the message fills n complete segments, where n?N. A known bit pattern is placed on any segments preceding a start of the message as determined by a start indicator. A first intermediate CRC code is computed for the n segments of the initial portion by applying the W bits of the bus forming an input word to a CRC full processing circuit using a compensating constant to compensate for any known bit pattern preceding the initial portion of the message. Subsequent portions of the message width W are placed on the bus during subsequent bus cycles, and in each case a new first intermediate CRC code is computed on the W bits of the bus as input words using the current first intermediate CRC code as a seed input.

Abstract: An apparatus consisting of a digital communication channel comprised of a multiplicity of lanes where data is striped across the lanes in a predefined sequence. Each lane has the ability to be powered down or powered up in response to the amount of data being held in a transmit buffer at one end of the communication channel. The method consists of monitoring the amount of data being held in the transmit buffer; making the decision of how many lanes are required based on the amount of data; sending signals to cause the required number of lanes to be powered down or powered up; and performing the required power down or power up action at the particular transmitter and receiver.

Abstract: Serial data streams received on multiple data lanes, wherein each data stream is in the form of a series of blocks including a data block preceded by a synchronization block, are deskewed by setting a detection flag in response to the valid detection of one or more synchronization blocks in each data stream, writing received data following the setting of said detection flag for that data stream to memory, and reading data sequentially from each memory under the control of a common output clock in response to the setting of the flag in respect at least a group of the data streams.