Patents Assigned to Saratoga Speed, Inc.
  • Patent number: 9384147
    Abstract: A system comprises a host device and a cache controller. The host device includes a command buffer and a host application that posts a cache command that includes a cache key and a key aging alias in the command buffer. The cache controller includes logic circuitry configured to load the cache command from the command buffer of the first host device into the buffer memory, identify a match, if any, for the cache key in the command queue, perform the cache command, and return cache completion status information to the first host application, wherein the cache completion status information includes a value of the key aging alias in cache metadata when a match for the cache key is found and includes a value of the key aging alias provided by the first host application when a match for the cache key is not found.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 5, 2016
    Assignee: Saratoga Speed, Inc.
    Inventors: Abbas Morshed, Chuan-Wen George Tsang, Christopher Youngworth
  • Patent number: 9304902
    Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 5, 2016
    Assignee: Saratoga Speed, Inc.
    Inventors: Sharad Mehrotra, Jack Mills, Chris Youngworth, Jon Livesey, Julian Ratcliff, Tim Lieber, Paul Sweere
  • Patent number: 9286225
    Abstract: Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 15, 2016
    Assignee: Saratoga Speed, Inc.
    Inventors: Sharad Mehrotra, Jack Mills, Thomas Gourley, Jon Livesey
  • Publication number: 20150006846
    Abstract: A method of storing a file in a storage system that includes a plurality of memory-storage hosts includes: specifying a unique chunk identifier for a memory chunk included in the file; specifying a hash mapping to identify one or more storage locations for the chunk identifier, each storage location corresponding to a portion of a memory-storage host; providing metadata corresponding to the hash mapping to the memory-storage hosts; and storing the memory chuck at the one or more storage locations identified by the hash mapping by providing the chunk identifier to one or more memory-storage hosts corresponding to the identified one or more storage locations, the one or more memory-storage hosts implementing the hash mapping to store the memory chunk at the identified one or more locations.
    Type: Application
    Filed: March 14, 2014
    Publication date: January 1, 2015
    Applicant: SARATOGA SPEED, INC.
    Inventor: Chris Youngworth
  • Publication number: 20140281153
    Abstract: Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices.
    Type: Application
    Filed: June 28, 2013
    Publication date: September 18, 2014
    Applicant: Saratoga Speed, Inc.
    Inventors: Sharad Mehrotra, Jack Mills, Thomas Gourley, Timothy Lieber