Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry is provided herein. In one embodiment, a circuit for protecting an integrated circuit from ESD includes a protected circuit node in the integrated circuit, a multiple stage transistor pump circuit coupled to the protected circuit node, and an electrostatic discharge protection circuit having a trigger coupled to the multiple stage transistor pump circuit. The multiple stage transistor pump circuit may comprise a Darlington transistor pump circuit.

Abstract: An apparatus having an inter-domain electrostatic discharge (ESD) protection circuit for protection of an integrated circuit (IC) with multiple power domains. The protection circuit in response to an ESD event provides an ESD protection between different power domains. Specifically, the protection circuit comprises at least one clamp coupled to one power domain, which conducts current during an ESD event to provide extra current in the interface line between the two different power domains. This extra current also in turn increases the voltage over the impedance element on the interface line, thus improving the design margins for the ESD protection and providing a better ESD protection capability for IC products.

Abstract: The present invention provides an improvement on ESD protection circuitry by controlling the trigger circuit to prevent the unwanted triggering of the device. The circuitry includes an ESD clamp with a trigger circuit coupled to the clamp. Both the clamp and the trigger circuit are coupled to a first reference potential. The circuitry also includes a control line coupled to the trigger circuit. The control line is coupled to a second reference potential to further control the behavior of the trigger circuit such that when the power is supplied to the second reference potential, the control line disables the trigger circuit, and when power is not supplied to the second reference potential, the control line enables the trigger circuit.

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.

Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages.