Patents Assigned to SAtech Group A.B. Limited Liability Company
  • Patent number: 7990958
    Abstract: A number of hash tables are accessed concurrently with a different computed index based on a single search key for each hash table. Each index identifies a location in one of the hash tables capable of storing at least one entry. If all indexed locations are used, the entries stored in the lookup table can be reordered so that the new entry can be inserted in one of the locations identified by the computed indexes.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: August 2, 2011
    Assignee: SAtech Group, A.B. Limited Liability Company
    Inventor: David A. Brown
  • Patent number: 7966421
    Abstract: A lookup table provides a longest prefix match for a search key longer than a lookup table's mapper key. The lookup table performs a multi-level search in one or more mappers for the result value based on a portion of the search key provided as the mapper key. The lookup table is searched in multiple passes with successive portions of the search key until the result value is found.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: June 21, 2011
    Assignee: SAtech Group, A.B. Limited Liability Company
    Inventor: David A. Brown
  • Patent number: 7913060
    Abstract: A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: March 22, 2011
    Assignee: SAtech Group, A.B. Limited Liability Company
    Inventor: David A. Brown
  • Patent number: 7895460
    Abstract: Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: February 22, 2011
    Assignee: SAtech Group, A.B. Limited Liability Company
    Inventors: Terence Neil Thomas, Stephen J. Davis
  • Publication number: 20110010564
    Abstract: Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.
    Type: Application
    Filed: September 17, 2010
    Publication date: January 13, 2011
    Applicant: SAtech Group, A.B. Limited Liability Company
    Inventors: Terence Neil Thomas, Stephen J. Davis
  • Patent number: 7558909
    Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: July 7, 2009
    Assignee: Satech Group A.B. Limited Liability Company
    Inventors: Alan Roth, Robert McKenzie, Oswald Becca
  • Patent number: 7423981
    Abstract: A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is provided to the first set of routes stored in a first memory space in the lookup table. Access is provided to the first memory space through a first pointer stored in a subtree entry. After storing the second set of routes in the second memory space, access is switched to the first set of routes in the first memory space by replacing the first pointer stored in the subtree entry with a second pointer to the second memory space.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: September 9, 2008
    Assignee: SAtech Group A.B. Limited Liability Company
    Inventor: David A. Brown