Abstract: A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The pipeline comprises four stages: an instruction fetch stage, an operand fetch stage, an execution stage, and a write back stage. In a first embodiment, an entire clock cycle is dedicated to the instruction fetch stage to the instruction fetch stage to retrieve instruction data from non-volatile memory in a single clock cycle. In a second embodiment, the operand fetch stage preliminarily decodes the instruction data to determine tasks to be performed to allow the execution stage to perform its time-intensive calculations in a single clock cycle. Additionally, the operand fetch stage initiates the performance of tasks determined from the decoding of the instructions to minimize the time required to perform those tasks by the execution stage.

Abstract: A system and method for efficiently handling interrupts in a microcontroller environment is disclosed. An interrupt handling circuit preserves a current state of a microcontroller comprising a plurality of primary registers for storing information relating to the current state of the microcontroller and a plurality of shadow registers coupled to at least two of the primary registers for storing the information contained in the coupled primary registers in response to receiving an interrupt enter signal from an interrupt signal generator. In one embodiment the information relating to the current state of the microcontroller includes the program counter, accumulator data, CPU status data, and an address pointer to data memory. In a preferred embodiment, the information is restored to the primary registers within one clock cycle of receiving an interrupt exit signal from the interrupt signal generator.

Abstract: An in-system debugging (ISD) capability is incorporated into a production microcontroller. The ISD capability is incorporated without the costly addition of any extra pins to read out the data for debugging by using the oscillator pins of the production microcontroller to read out the data. Building such an ISD capability into the microcontroller, enables debugging to be performed on the actual production board (instead of a special debug board) having the actual production microcontroller (instead of a bond-out microcontroller). This allows designers to debug programming using the actual production system instead of an emulation system.

Abstract: A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.

Abstract: A method and apparatus for In-System Programming which overcomes the above-described disadvantages. The method and apparatus of the ISP system interfaces with the two oscillator (instead of I/O) pins on the microcontroller. By interfacing with the two oscillator pins, the need for extra isolation circuitry to isolate other circuits from the ISP circuits is avoided in most circumstances, without incurring the expense of an expensive JTAG tester or extra dedicated pins. The amount of isolation circuitry necessary is reduced because the two oscillator pins are usually connected to passive components (registers, capacitors, or crystals) which cannot be damaged by the relatively high programming voltages and which do not produce signals that would interfere with the ISP programming signals.

Abstract: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

Abstract: A system and method for detecting brown-out conditions in a microcontroller, enabling a user to program the brown out detection system, and distinguishing between real brown-out events and transitory voltage swings without requiring expensive and time consuming logic. The invention compares a sense voltage to a reference voltage and filters the resulting signal to distinguish between a true-brown out signal and transitory voltage swings. The invention uses one or more program bits that vary the ratio of the supply voltage and the sense voltage. That is, the sense voltage is programmable and is dependent upon the value of the supply voltage and the value of the program bits. The present invention generates a comparison output signal based upon the comparison of the supply voltage and the sense voltage. The comparison output signal is filtered to distinguish between a real brown-out event and transitory voltage swings.

Abstract: A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new address points to a new instruction in a program memory. The program instruction data is read from the program memory into an instruction register and then transferred from the instruction register to the word register and the mode register. The contents of the word register and the mode register are then written to a data memory. With the program instruction data now available in the data memory, the new instruction can be tested for data integrity and validity using, for example, fault detection mechanisms or processes. A system for fault detection to check instructions or data in the program memory for data integrity and validity in a program memory also is disclosed.

Abstract: A system and method for ensuring a substantially constant oscillator frequency that is substantially independent of the operating temperature and is substantially independent of variations of the supply voltage level where the oscillator is an on-chip oscillator without requiring significantly additional logic, e.g., not requiring the use of multiple comparators and enabling post packaging modifications of the oscillator frequency. The present invention utilizes one or more paired resistors as part of the RC oscillator where each of the one or more pairs are matched according to their temperature coefficient. That is, each pair includes a resistor with a positive temperature coefficient and a resistor with a corresponding negative temperature coefficient. In addition, the present invention enables post packaging modifications to the resistors based upon one or more program signals that can modify the resistance by forming a short circuit around one or more resistor pairs.