Abstract: A method for directly measuring the area of a topological surface with an arbitrary boundary shape lying in a fixed elevation different from a fixed surrounding surface elevation relies upon binocular stereo vision. Three stereo correlation measurements are made, one over a window entirely within the surface of interest, a second over a window outside the surface of interest and within the surrounding area, and a third over a window fully containing the surface of interest as well as some of the surrounding area. The correlation measured in the third case is the linear sum of the correlation value over each of the first two cases weighted by the proportion of the window that the two surfaces occupy.

Abstract: A system for shape recognition includes a spatial convolution filter which has an approximately band pass response. The filter is applied to a camera image and the sign of the filter's output is used to produce a second binary image. At sufficiently coarse (low center spatial frequency) scales, this image tends to change isolated shapes into single blob-shaped regions. The same convolution operator is then reapplied to this binary signal blob image and peaks in the output of the second convolution are used as the primitive elements for building a shape description. By processing the image with operators of two different scales the peaks shift position. The location of peaks from the coarse scale operator together with vectors to the fine scale peaks provide a description of the shape for a look-up table or other system.

Abstract: A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing signals representing leading edge and trailing edge markers precisely within each period. The period circuit comprises a period-end memory having a plurality of storage locations which are addressed by a modulo(n) counter. To support multiple timing sets, or timing cycles, one or more of the most significant bits of the address field for the period-end memory may be reserved for designating each timing signal. The time interval measured by the period-end memory may be selectively extended by delaying the clocking signal used for incrementing the modulo(n) counter.

Abstract: A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information representing the higher order bits of a time delay, while vernier memories store information relating to the lower order bits of the time delay. Offset memories enable storing calibration data. The base delay memory controls at least two counters in independent signal paths, while the vernier and offset memories control appropriate deskew units for further delaying the counter output signal as desired. The system enables sharing of resources, yet eliminates the need for repetitively loading correction data for deskew operations.

Abstract: A system for determining the s-plane parameters, s.sub.i and r.sub.i, of the transient response, ##EQU1## of a network-under-test (NUT). A filter bank, including N serially connected filter elements, has an input port and N output ports being the output ports of the filter elements. The system includes circuitry for sampling the response signal, at the N filter bank output ports. T seconds after a transient signal is received at the input port. A processor utilizes the values of the sampled response signal to determine the values of s.sub.i and r.sub.i.

Abstract: Apparatus for delaying an electrical signal includes a sequence of stages, each for delaying the signal. A coarser stage delays the signal by multiples of a predetermined fundamental delay interval and a finer stage provides for fine adjustment of the delay. The fine stage includes an integral number N of delay elements, the total providing a delay interval greater than the fundamental delay interval, whereby the fine delay intervals compensate for fabrication tolerances to enable accurate calibration of the combined system by post-fabrication measurement. In one implementation each delay stage includes a tapped transmission line to provide delay intervals, in another a ramp generator is used.

Abstract: A video stream processing system comprising a novel modular family of image processing and pattern recognition submodules, the submodules utilize a unique system signalling and interface protocol, and thus can be cascaded and paralleled to produce complex special purpose image processing systems which can operate at video or near video data rates. A stream of digitized pixel data is pipelined through a variety of submodules to support a wide variety of image processing applications. A common video interface provides for handling pixel data in the video signal path and a processor interface allows communication to any modern microprocessor for overall system control, for optional addition image processing and for defining options within each submodule.

Abstract: A video stream processing system frame buffer controller for controlling external dynamic random access memory (DRAM) of a frame buffer and interfacing to the video stream processing signal bus. The frame buffer controller has four interfaces, video input interface, video output interface, memory interface and processor interface. The circuit can input image data from a camera and store the frames in external DRAM. The circuit provides for external processor access to pixels in the frame buffer and for output of the frame or portions of the frame, as well as output of frames in a format of CRT display and external DRAM refresh.

Abstract: An improved computer memory system based on a novel four transistor memory cell and an improved address decoder circuit is disclosed. The memory cell can be fabricated using currently available logic fabrication processes and requires a silicon area less than that required by prior art static memory cells. The improved decoder can be fabricated in significantly less silicon area than existing NOR gate decoder arrays and is faster than existing NOR gate decoder arrays.

Abstract: A multi-marker, multi-destination timing signal generator including a count-setting memory for storing a plurality of pulse-count values in a numerical order and a pulse counter for counting the number of pulses from a master clock. An output selection memory stores, for each pulse count value, enabling signals for a plurality of output elements so that a marker signal generated when the pulse counter equals a pulse-counter value in memory may be selectively routed to one or more output elements. The addresses of the count-setting memory and the output selection memory are maintained by an address counter. When the value of the pulse counter equals a pulse-count value stored in the count-setting memory, the address counter counts to the next address value for locating successive values in the count-settiong memory and the output selection memory.

Abstract: An image processing system for computing morphological characteristics of object regions in a binary image frame. The characteristics are generated at the frame rate. One embodiment utilizes an architecture including an interconnected delay component, bit packing component and LUT. The output values provided by the LUT are accumulated over one frame cycle to compute morphological characteristics.

Abstract: A high precision analog to digital converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compensate for errors of any bit combination. In a specific embodiment employing feedback compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a video camera. The processing of a frame of image data by each circuit component is simulated and the resulting frames of image data are stored until they are no longer needed by other components. The output of the simulated circuit is displayed on a monitor.The timing of the circuit is analyzed for distinct groups of components which must operate in synchronism. Scaling factors are calculated for each net in the group from the incremental scaling rate of each component and the connectivity of the circuit. The scaling factors indicate the relative rate at which value pixels arrive at each net. The time at which a reference pixel arrives at each net is then computed to ensure that corresponding pixels arrive together at components with multiple inputs.

Abstract: An arithmetic logic system for performing a variety of arithmetic and logical functions on pixel input streams such as averaging down the input image stream, computation of absolute values, and signed or unsigned, clipped or unclipped, addition, subtraction and multiplication. The arithmetic logic system has a first arithmetic logic unit connected to a plurality of input signals. A second arithmetic logic unit is coupled to the first arithmetic logic unit and operates on the output of the first arithmetic logic unit. A control unit is coupled to the first and second arithmetic logic units and controls the operation of the second arithmetic logic unit based on the output of the first arithmetic logic unit.

Abstract: A processing element may be used either separately or in an array of similar processing elements for performing concurrent data processing calculations. The processing element includes a multiported memory unit for storing data to be processed by any of a plurality of function units which are connected to the multiported memory unit. The multiported memory unit includes a number of data storage slots for storing data words to be processed and the results of said processing. Each function unit performs a calculation having as its inputs one or or more data words from the multiported memory unit. The result of this calculation is stored back in the multiported memory unit. The transfer of data to and from the function units is accomplished by use of the ports on said multiported memory unit. The data manipulated by the processing element is controlled by specifying a correspondence between data storage slots, memory input ports and memory output ports.