Abstract: A logic system which includes a plurality of identical logic circuit building blocks, each referred to as an M Circuit, is disclosed. The M Circuits are connected in a linear array of interconnected M Circuits including first through last M Circuits, the linear array providing a latch operation. The system comprises a plurality of M Circuits each of which responds to transitions of a two-level binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B. Each of the M Circuits comprises a gate having two inputs connected to the A and B input terminals, resepectively, and a set-reset flip flop having its set input connected to the output of the gate, the reset input connected to the B input terminal and the set and reset outputs connected, respectively, to the output terminals Q and Q of the M Circuit.
Abstract: A logic circuit building block, referred to as an M Circuit, is provided which solves various problems of prior art logic circuit building blocks and binary logic systems. The M Circuit responds to transitions of a two level binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B. The M Circuit generally includes both logic gating and a memory for placing the M Circuit in a set condition in response to the application of first known combinations of input signal levels or transitions at the A and B terminals, and for placing the M Circuit in a reset condition in response to the application of second known combinations of input signal levels at the A and B input terminals.
Abstract: A logic system includes first and second identical logic circuit building blocks, each referred to as an M Circuit, which responds to transitions of a two level, binary input signal to provide a memory and a logic function which has a complete truth table for every possible combination of input signal transitions or changes in logic level at a pair of input terminals A and B.