Abstract: Disclosed is a computer system which includes multiple levels of bootstrap code. The first level of bootstrap code is stored in a non-volatile storage means associated with a host processor. A second non-volatile storage means is provided which stores a second level of bootstrap code. A processor means, separate from the host processor, controls access by the host system to both the first and second non-volatile storage means. The second non-volatile storage means in the preferred embodiment is electrically writable and erasable by the host computer system, by the processor means associated with the second non-volatile storage means, or by an input device provided for that purpose.

Abstract: A compact chassis-integrated slide assembly for use with electronic or other equipment. A movable chassis is translated relative to a stationary rack. Two or more slide guides are fastened to each of the two side walls of the chassis. The slide guides are adapted to slidably engage a channel in a floating slide member. The floating slide member supports the chassis while at the same time permitting relative translation of the chassis and the floating slide by means of the slide guide sliding in the channel of the floating slide. The floating slide in turn slidably engages a rack sheath where the rack sheath is adapted to be rigidly attached to the stationary rack.

Abstract: A second order filter signal is derived in response to a phase comparison of two signals by selecting an input voltage from a reference voltage, a first voltage potential higher than the reference voltage, and a second voltage potential lower than the reference voltage depending on the phase error of the two signals. The input signal is applied to a loop filter including a non-inverting integrator and to a feed forward circuit. The outputs of the amplifier and feed forward circuit are summed and applied to an output terminal as the second order filter signal. An improved phase locked oscillator circuit is provided in which a digital phase comparator drives an active loop filter including a feed forward circuit and a non-inverting integrator.

Abstract: Semiconductor structure having a plurality of isolated islands in which semiconductor devices are formed and which are interconnected to form an integrated circuit. The islands are isolated from each other by a combination of dielectric isolation in the form of moats and regions of higher conductivity extending downwardly into the semiconductor body from the moats. The semiconductor body from which the semiconductor structure is formed has a surface with a <100> orientation. An etch resistant mask is formed on the surface. An anisotropic etch is utilized to provide a plurality of isolation moats extending downwardly from the surface and having inclined side walls oriented along a crystal plane different from the <100> plane and having bottom walls oriented along the <100> crystal plane of the semiconductor body. The side walls and the bottom walls of the moats are oxidized. The oxide on the bottom walls is then removed.

Abstract: A data processing system in which a programmed supervisor data processing machine and a programmed object data processing machine are interconnected. The object machine is typically a controller which receives input signals from and delivers output signals to interface vector buffer stores under control of an object machine program. The buffer stores connect to and from user devices. The supervisor machine operates to execute a supervisor machine program. The supervisor machine halts and starts the object machine, causes supervisor instructions to be executed in the object machine, extracts information from the object machine and restores the object machine to its prehalt status allowing the object machine to continue processing the object machine program.

Abstract: Disclosed is a controller which functions to interconnect and control one or more digital devices such as magnetic discs, typewriters and other digital data processing equipment. The controller receives input signals and delivers output signals through interface vector (IV) buffer stores which connect to and from user devices. The logical state of the output signals in the buffer stores is determined by an instruction-controlled processor which accesses instructions from a memory. The instructions are processed in response to input signals (operands) from buffer stores and produce output signals (operands) to the buffer stores. The instruction fetching paths and the operand fetching and storing paths are separate. The controller includes apparatus and an instruction set which allows variable fields in the buffer stores to be addressed to provide source operands and to be addressed to store result operands after instruction execution.