Abstract: A system includes a crest-factor reduction circuit, a signal analyzer, and a pre-distortion circuit. The crest-factor reduction circuit reduces a crest factor of a baseband signal and generates a feedforward signal. The signal analyzer generates parameters based on the feedforward signal and an output signal from a power amplifier. The pre-distortion circuit generates a pre-distorted baseband signal based on the parameters for input to the power amplifier.

Abstract: A transceiver coupled to an antenna includes: (a) a multi-port filter having a bidirectional port coupled to the antenna, at least one input port and at least one output port; (b) a transmit datapath receiving a transmission signal and providing the transmission signal for transmission by the antenna through the multi-port filter, the transmit datapath being coupled to the input port of the multi-port filter; (c) a receive datapath receiving a reception signal from the antenna, the receive datapath being coupled to the output port of the multi-port filter; (d) a band-pass filter coupled to the antenna for receiving a sampled signal that includes intermodulation components between two or more of an external signal, the transmission signal and the reception signal; and (e) a monitoring and cancellation circuit receiving the transmission signal, the reception signal and the sampled signal to cancel the intermodulation components.

Abstract: A filter enhancer provides greater performance in a passive filter. The passive filter has an input terminal for receiving a signal in a first frequency band and an output terminal for providing a signal in a second frequency band. The filter enhancer includes: (a) a first canceller circuit coupled between input terminal and output terminal, the first canceller circuit including a first finite impulse response (FIR) filter for attenuating signals in the first frequency band; and (b) a control circuit coupled to output terminal and first canceller circuit for providing adaptive coefficients for configuring the first FIR filter. The first FIR filter may be implemented by either a digital FIR filter or an analog FIR filter. The filter enhancer may further include a second canceller circuit coupled between input terminal and output terminal, the second canceller circuit including a second FIR filter for attenuating signals in the second frequency band.

Abstract: A crest factor reduction (CFR) circuit reduces the peak-to-average (PAR) power of a digitally modulated signal in a complex baseband is achieved by post-processing the input signal, with negligible increase in out-of-band emissions. The CFR circuit takes advantage of a procedure that solves for an optimum CFR using a constraint-optimization approach. In one embodiment, the CFR circuit, which receives an input signal and provides an output signal, includes: (a) an error generation circuit that receives the input signal and provides an error signal representative of a measure of circuit-induced distortion and a delayed input signal, the delayed input signal being the input signal delayed by a predetermined value; (b) a linear-phase filter receiving the error signal to provide a correction signal; and (c) a summer that subtracts the correction from the delayed input signal to provide the output signal.

Abstract: A system for implementing linearization of a radio frequency (RF) power amplifier (PA) in a base station, as well as various component circuitry for implementing said system. By means of a smart partitioning of the signal processing for predistortion between the analog domain and the digital domain, a more linear relationship between the digital input data and the output RF signal is achieved. Linearization of the PA's output signal is obtained using a mixed-signal apparatus. The digital baseband signal enters the RF signal source. The RF signal source comprises an in-band predistortion circuit, a micro-controller and digital modulator. The output of the digital modulator is an RF signal that enters the PA module. The PA module is composed of the PA and the RF power amplifier linearizer (RFPAL). The RFPAL comprises an RF predistortion circuit, and RF signal analyzer and a microcontroller. In addition, a backward data interface connects the RF signal source with the RFPAL.

Abstract: An RF linearizer and an associated method are provided for linearizing a power amplifier. The RF linearizer may include: (a) a quadrature up-converter for up-converting a baseband input signal that is to be transmitted by the power amplifier; (b) an RF analog predistorter controlled by a set of coefficients for predistorting the up-converted input signal; (c) a down-converter for down-converting an output signal of the power amplifier; (d) an error monitor receiving the down-converted output signal and the input signal for providing an error signal; and (e) a signal analyzer receiving the error signal, the signal analyzer using an out-of-band power spectrum of the error signal to optimize the set of coefficients. The input signal may have an in-phase component and a quadrature component.