Abstract: Convergent and extrapolated samples are provided for synthesizing sine waves. In a first embodiment, memory having the sine function, sin(x), mapped therein provides convergent samples. Memory size is reduced in a second embodiment by summing the outputs of two memories to produce convergent samples, one memory having an auxiliary function, f(x), mapped therein and a second having the sine function less the auxiliary function, sin(x)-f(x), mapped therein. A sine wave quadrant is conceptually divided into a plurality of uniform phase sectors demarked by boundaries phases. Additional memory provides extrapolation value sets uniquely associated with the sectors. In a given sector, extrapolation samples are produced by serially adding values of the associated extrapolation set to the convergent samples selected in the sector.

Abstract: A fractional divider using a counter means to provide fractionality. A divider is used to divide the VCO output signal by N or N+1 as selected. A divider control circuit controls the divider to divide by the appropriate divisor to obtain the selected output frequency. The fractional divider circuit counts divider control signals which represent a first division period. The fractional divider circuit establishes a second period of multiple first periods and at the terminal count of each second period, provides a selected number of fractional control signals to the divider control to cause division by a different number, such as N+1. The fractional divider comprises a first counter programmed to count first periods and issue its terminal count upon receiving the programmed count of first periods. The fractional divider also comprises a second counter to provide the selected number of fractional control signals upon receipt of the terminal count of the first counter.

Abstract: An improvement in a frequency synthesizer having a generator which produces mix frequencies and at least one mix and filter stage, said stage having a frequency divider. The improvement comprising: (1) a frequency divider for producing a periodic signal the frequency of which is an integer divisor of the mix frequencies, (2) a one-shot for producing an enabling signal whenever a change occurs in the selection of the frequency being synthesized, the duration of the enabling signal being sufficient to ensure coincidence of it and said periodic signal, and (3) a coincidence gate for resetting the frequency divider of each mix and filter stage to a predetermined state whenever there is a coincidence of the enabling signal and the periodic signal.

Abstract: N stages of BCD adders receive as a first addend BCD encoded information representing a desired frequency. They receive as a second addend the outputs of N stages of four-bit registers. The summing outputs of the adders are input data for the registers. The data is clocked into the register by a stable frequency source. The outputs from a plurality of the most significant stages of the registers are used to address a ROM. Using the periodically changing BCD address, a sinusoidal function is retrieved in individual samples from the ROM. Digital data from the ROM is converted to analog. A low pass filter enhances the desired frequency and suitably attenuates higher frequencies. An equalizer compensates for power roll-off.