Abstract: A bond pad set includes at least one ground pad and at least one electrical bond pad configured to bias and send/receive signals. The bond pad set is electrically connected to a multiplicity of electrical components. At least one electrical bond pad of the bond pad set is shared between two or more of the electrical components.

Abstract: An apparatus may include a circuit that performs one or more read and recovery operations for one or more data segments including updating an outer code syndrome for one or more recovered data segments recovered by the one or more read and recovery operations and preventing updates of the outer code syndrome for one or more failed data segments not recovered by the one or more read and recovery operations.

Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

Abstract: A folded lasing cavity comprises at least one bend. The folded lasing cavity is disposed on and configured to emit light along a substrate-parallel plane. An etched facet is on an emitting end of the folded lasing cavity and an etched mirror is on another end of the folding lasing cavity. An etched shaping mirror redirects light received from the etched facet in a direction normal to the substrate-parallel plane.

Abstract: Systems and methods are disclosed for management of a tiered storage system by a top tier storage device. In some embodiments, an apparatus may comprise a circuit configured to maintain an address map at a first storage tier, receive a read request for specified data, return the specified data when the data exists on the first storage tier, and when the specified data does not exist on the first storage tier, return an indication to query a second storage tier. The circuit may be further configured to determine infrequently accessed cold data stored to the first tier, provide to a host device a copy of the cold data stored in an area of the first storage tier scheduled for defragmentation, and perform the defragmentation operation, including copying valid data to an available area of the first storage tier, the valid data not including the cold data.

Abstract: In response to a cacheable write request from a host, physical cache locations are allocated from a free list, and the data blocks are written to those cache locations without regard to whether any read requests to the corresponding logical addresses are pending. After the data has been written, and again without regard to whether any read requests are pending against the corresponding logical addresses, metadata is updated to associate the cache locations with the logical addresses. A count of data access requests pending against each cache location having valid data is maintained, and a cache location is only returned to the free list when the count indicates no data access requests are pending against the cache location.

Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.

Abstract: A write head comprises a waveguide core configured to receive light emitted in a crosstrack direction from a light source at a fundamental transverse electric (TE00) mode. The waveguide core comprises a first turn that receives the light in the crosstrack direction redirects the light to an opposite crosstrack direction and a second turn that redirects the light to a direction normal to a media-facing surface of the write head. The waveguide core comprises a straight section that couples the first and second turns and a branched portion extending from the straight section. The branched portion is configured to convert the light to a higher-order (TE10) mode. A near-field transducer at the media-facing surface is configured to receive the light at the TE10 mode from the waveguide and directs surface plasmons to a recording medium in response thereto.

Abstract: A near-field transducer is situated at or proximate an air bearing surface of the apparatus and configured to facilitate heat-assisted magnetic recording on a medium. The near-field transducer includes an enlarged region comprising plasmonic material and having a first end proximate the air bearing surface. The near-field transducer also includes a disk region adjacent the enlarged region and having a first end proximate the air bearing surface. The disk region comprises plasmonic material. A peg region extends from the first end of the disk region and terminates at or proximate the air bearing surface. The near-field transducer further includes a region recessed with respect to the peg region. The recessed region is located between the peg region and the first end of the enlarged region.

Abstract: A system includes a first optical communication interface and a second optical communication interface optically coupled via a free-space communication channel. The interfaces are spaced at variable distances. Each interface includes an optical source to provide a beam of electromagnetic energy and an optical receiver to receive the beam to bi-directionally communicate with the other interface via the channel. The first optical communication interface may be coupled to a sub-chassis. The second optical communication interface may be coupled to a device frame. The device frame may be movably coupled to the chassis. Communication may utilize multi-input, multi-output processing configured by a calibration matrix. A shutter may be positioned to receive the beam or be positioned clear of the beam depending on the distance between the interfaces.

Abstract: Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.

Abstract: As may be implemented in accordance with one or more embodiments, an electrical connector such as a low-temperature co-fired ceramic (LTCC) connector is sealed to an opening in a base deck having bottom and/or side walls that define a cavity. A mechanical component is coupled to balance forces applied to opposing surfaces of the electrical connector, which can mitigate the application of high forces to connector pins and/or to the connector itself. Further, this balancing may be implemented to maintain a controlled bias force against the connector. The electrical connector may, for example, be hermetically sealed to the opening by a seal such as a gasket, epoxy or other material, which may be included in the electrical connector.

Abstract: A preamplifier may have a freeze bit that when set, puts the preamplifier in a static state, which prevents the preamplifier from implementing subsequent programming commands. The freeze state may continue until an unfreeze bit is programmed. In a multiple preamplifier system, preamplifiers can be differently and individually configured over a single interface. Preamplifiers may be released from the static state (frozen) by either programming the unfreeze bit (which can release all of the preamps) or by programming the freeze bit to a “0” state (releases the individual preamp). An inversion control circuit can allow inversion of a control signal to a preamplifier. The inversion control circuit may be enabled and disabled based on a physical conductive connection to a logic high voltage or a logic low voltage. One or more programmable control lines can determine whether the inversion function is activated when the inversion control circuit is enabled.

Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.

Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

Abstract: An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.

Abstract: An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.

Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

Abstract: A slider includes an array of two or more transducer sets offset from one another in a cross-track direction. Each transducer set includes at least one writer and at least one reader. All of the transducer sets are configured to operate simultaneously to perform any combination of reading and writing on two or more tracks of a recording medium. At least one actuator is included between two the transducer sets. The actuator is configured to adjust a cross-track spacing between the two transducer sets in response to a control current.