Abstract: The embodiments disclose a stack feature of a stack configured to confine optical fields within and to a patterned plasmonic underlayer in the stack configured to guide light from a light source to regulate optical coupling.
Type:
Application
Filed:
October 16, 2013
Publication date:
January 15, 2015
Applicant:
SEAGATE TECHNOLOGY LLC
Inventors:
Ganping Ju, Chubing Peng, Xiaobin Zhu, Yingguo Peng, Yukiko A Kubota, Timothy J Klemmer, Jan-Ulrich Thiele, Michael A. Seigler, Werner Scholz, Kim Y. Lee, David S. Kuo, Koichi Wago
Abstract: An apparatus includes an input region having a high-refractive-index material and an input surface configured to receive light emitted from a laser. An output surface of the apparatus is configured to deliver energy to a recording medium. The apparatus includes a plasmonic waveguide having a first elongated portion at an angle to the input surface and configured to receive the light through the input region. In response to receiving the light, surface plasmons are excited and guided to an end of the first elongated portion. The plasmonic waveguide includes a second elongated portion coupled to the end of the first elongated portion and configured to guide the surface plasmons to the output surface.
Abstract: Provided herein is a method including oxidizing tops of features of a patterned magnetic layer to form oxidized tops of the features; removing an excess of an applied first protective material down to at least the oxidized tops of the features to form a planarized layer; and applying a second protective material over the planarized layer.
Type:
Application
Filed:
October 24, 2013
Publication date:
January 15, 2015
Applicant:
Seagate Technology LLC
Inventors:
Michael R. Feldbaum, Wago Wago, Bin Lu, David S. Kuo
Abstract: The embodiments disclose at least one predetermined patterned layer configured to eliminate a physical path of lateral thermal bloom in a recording device, at least one gradient layer coupled to the patterned layer and configured to use materials with predetermined thermal conductivity for controlling a rate of dissipation and a path coupled to the gradient layer and configured to create a path of least thermal conduction resistance for directing dissipation along the path, wherein the path substantially regulates and prevents lateral thermal bloom.
Type:
Application
Filed:
October 16, 2013
Publication date:
January 15, 2015
Applicant:
SEAGATE TECHNOLOGY LLC
Inventors:
Ganping Ju, Xiaobin Zhu, Chubing Peng, Yukiko A. Kubota, Yingguo Peng, Timothy J. Klemmer, Jan-Ulrich Thiele, David S. Kuo, Bin Lu, Julius K. Hohlfeld
Abstract: In certain embodiments, an apparatus includes a first piezoelectric (PZT) element poled in the same direction as a second PZT element. The first and second PZT elements are configured to be driven while simultaneously sensing motion. The apparatus further includes a circuit configured to add outputs of the first and second PZT elements, extract the sensed motion, and detect off-track motion from the extracted sensed motion.
Type:
Grant
Filed:
December 15, 2011
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Narayanan Ramakrishnan, Stefan Alexander Weissner
Abstract: Technologies are described herein for recovering an instable head in a storage device using an internal head heater. An instability in the reader head may be detected, and, in response to detecting the instability, a thermal shock may be applied to the reader head utilizing the head heater to recover the head.
Type:
Grant
Filed:
December 21, 2012
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Jung Wook Hur, Won Choul Yang, Haejung Lee
Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
Type:
Grant
Filed:
February 26, 2013
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Ara Patapoutian, Ryan James Goss, Antoine Khoueir
Abstract: A method including forming a multilayer structure. The multilayer structure includes a seed layer comprising a first component selected from the group consisting of a Pt-group metal, Fe, Mn, Ir and Co. The multilayer structure also includes an intermediate layer comprising the first component and a second component selected from the group consisting of a Pt-group metal, Fe, Mn, Ir and Co. The second component is different than the first component. The multilayer structure further includes a cap layer comprising the first component. The method further includes heating the multilayer structure to an annealing temperature to cause a phase transformation of the intermediate layer. Also a hard magnet including a seed layer comprising a first component selected from the group consisting of a Pt-group metal, Fe, Mn, Ir and Co. The hard magnet also includes a cap layer comprising the first component. The hard magnet further includes an intermediate layer between the seed layer and the cap layer.
Type:
Grant
Filed:
April 30, 2008
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Jiaoming Qiu, Younghua Chen, Xilin Peng, Shaun McKinlay, Eric W. Singleton, Brian W. Karr
Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
Type:
Grant
Filed:
October 17, 2011
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
Abstract: An apparatus including a near field transducer positioned adjacent to an air bearing surface, the near field transducer comprising silver (Ag) and at least one other element or compound; a first magnetic pole; and a heat sink positioned between the first magnetic pole and the near field transducer, wherein the heat sink includes: rhodium (Rh) or an alloy thereof; ruthenium (Ru) or an alloy thereof; titanium (Ti) or an alloy thereof; tantalum (Ta) or an alloy thereof; tungsten (W) or an alloy thereof; borides; nitrides; transition metal oxides; or palladium (Pd) or an alloy thereof.
Type:
Grant
Filed:
October 24, 2013
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Jie Zou, Kaizhong Gao, William Albert Challener, Mark Henry Ostrowski, Vankateswara Rao Inturi, Tong Zhao, Michael Christopher Kautzky
Abstract: Technologies are described herein for adaptive write pole tip protrusion compensation in a storage device having magnetic recording media. Variations in temperature of a head of a storage device are measured for various combinations of values of write-channel parameters during multiple test writes to the recording media. Sensitivity of the head temperature to change in value of the write-channel parameters is determined from the temperature measurements. A ratio of change in write pole tip protrusion of the head to change in head temperature is also determined. From the sensitivity of the head temperature to change in value of the write-channel parameters and the ratio of change in write pole tip protrusion of the head to change in head temperature, a coefficient corresponding to each write-channel parameter is calculated for the head to be utilized in a write pole tip protrusion compensation mechanism of the storage device.
Type:
Grant
Filed:
September 25, 2013
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Shi Jung Kim, Won Choul Yang, Ju Yong Lee
Abstract: Thus, if a shock or other disturbance to a disc stack spindle bearing assembly occurs that tilts the bearing assembly, the resulting motion is both a tilting, and a motion which is axial. If a shock axially moves the hub assembly, only an axial motion occurs. Thus the system has a non-linear behavior. Pursuant to this invention, when a tilting disturbance occurs, and some of it is dissipated in a net axial movement at a different frequency, energy is subtracted out of the system with motion that is not linearly related to the disturbance that created it.
Type:
Grant
Filed:
September 14, 2012
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Hans Leuthold, Susan Immisch, Saul Ceballos, Michael Tiller
Abstract: A flex circuit including a multiple layer structure is disclosed. The multiple layered structure includes a first or top layer and a second or base layer. Top traces and bond pads are fabricated on the top or obverse layer and interlayer traces and bond pads are fabricated between the first and second layers to provide an electrical interconnect to electrical components on a head assembly. In an illustrated embodiment, the flex circuit includes portions including the first or base layer and the second or top layer and one or more reduced thickness portion including the first or base layer and not the second layer.
Type:
Grant
Filed:
March 15, 2013
Date of Patent:
January 13, 2015
Assignee:
Seagate Technology LLC
Inventors:
Ravishankar Ajjanagadde Shivarama, Bradley J. Ver Meer, Razman Zambri
Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.
Type:
Application
Filed:
April 29, 2014
Publication date:
January 8, 2015
Applicant:
SEAGATE TECHNOLOGY LLC
Inventors:
Antoine Khoueir, YoungPil Kim, Rodney Virgil Bowman
Abstract: Implementations disclosed herein allow a printed circuit board (PCB) to be removeably secured to a lapping carrier. The lapping carrier may include a clamping mechanism and one or more alignment pins that thread through corresponding holes in the PCB. In other implementations, the lapping carrier includes insulation that prevents current leakage or short-circuiting of electrical paths on the PCB during contact with the clamping mechanism.
Type:
Application
Filed:
July 2, 2013
Publication date:
January 8, 2015
Applicant:
Seagate Technology LLC
Inventors:
Kim Sek Tan, Choong Kit Mah, Soo Chun Loh, Choon Yen Lim, Chin Chong Yew, Leping Li, Yuik Zhi Lim
Abstract: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored.
Type:
Grant
Filed:
May 31, 2012
Date of Patent:
January 6, 2015
Assignee:
Seagate Technology LLC
Inventors:
Ryan James Goss, Mark Allen Gaertner, David Scott Seekins
Abstract: In certain embodiments, an apparatus includes a top shield, bottom shield, polarizer, nonmagnetic conductor layer, and a sensor stack having a first sensor layer. The sensor stack is positioned at a distance recessed from a first plane. The nonmagnetic conductor layer is positioned between the polarizer and the first sensor layer. A magnetization of the first sensor layer is arranged and configured to move in the same direction as a magnetization of the polarizer.
Abstract: A plasmonic transducer includes at least two metal elements with a gap therebetween. The metal elements are placed along a plasmon-enhanced, near-field radiation delivery axis. Cross sections of the metal elements in a plane normal to the delivery axis vary in shape along the delivery axis. The metal elements have a reduced cross section portion at a media-facing surface oriented normal to the delivery axis. A dielectric material surrounds the reduced cross section portion of the plasmonic transducer at the media-facing surface, and reduces deformation of the metal elements proximate the media-facing surface at elevated temperatures.
Abstract: A writer includes a write element having a tip portion to generate a write field during a write operation and a conductive assembly that delivers a write assist current through the tip portion in a cross-track direction to generate a write assist field during the write operation that extends beyond a medium confronting surface located at the tip portion to lower a coercivity of a magnetic medium proximate to the write element.
Type:
Grant
Filed:
March 15, 2007
Date of Patent:
January 6, 2015
Assignee:
Seagate Technology LLC
Inventors:
Chunhong Hou, Shaoping Li, John M. Wolf, Sining Mao
Abstract: A photovoltaic apparatus includes an absorber including a first quantum dot layer having a first plurality of quantum dots of a first quantum dot material in a first matrix material, and an up-converter layer positioned adjacent to the absorber layer, the up-converter layer including a second quantum dot layer having a second plurality of quantum dots of a second quantum dot material and a second matrix material.
Type:
Grant
Filed:
August 21, 2008
Date of Patent:
January 6, 2015
Assignee:
Seagate Technology LLC
Inventors:
Hans Jürgen Richter, Samuel Dacke Harkness, IV