Abstract: A recording head has a near-field transducer proximate a media-facing surface of the recording head. The near-field transducer extends a first distance away from the media-facing surface. A waveguide overlaps and delivers light to the near-field transducer. Two subwavelength focusing mirrors are at an end of the waveguide proximate the media-facing surface. The subwavelength mirrors are on opposite crosstrack sides of the near-field transducer and separated from each other by a crosstrack gap. The subwavelength focusing mirrors each include a first material at the media-facing surface and a liner that covers an edge of the mirror.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

Abstract: Systems and methods are disclosed for calibrating actuators in a multi-stage servo system. In certain embodiments, a method may comprise performing a calibration process on a multi-stage actuated servo system, including: seeking the multi-stage actuated servo system to a selected location, via a first stage actuator; providing a first voltage injection to a first microactuator of the multi-stage actuated servo system; measuring a first position error signal (PES) of the multi-stage actuated servo system; determining a first gain for the first microactuator based on the first PES, without adding a signal injection to the first PES; and applying the first gain to the first microactuator.

Abstract: A system includes a computing device with circuitry and memory with instructions for execution by the circuitry. The instructions include monitoring signals indicative of a non-uniform distance between a transfer head and a receiving substrate, and, in response to the monitored signals, actuating one or more actuators towards the transfer head or the receiving substrate to deform the transfer head or the receiving substrate.

Abstract: Initialization stripes of a redundant array of inexpensive disks (RAID) may include determining whether the stripes have already been initialized based on redundant correction information. Further, un-initialized stripes may be initialized before intended if write requests are received for such un-initialized stripes. Still further, rebuilt stripes (e.g., portions thereof) may also be checked to determine whether such rebuilt stripes have been initialized based on error detection codes.

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.

Abstract: A recording head includes a channel waveguide that delivers light to a media-facing surface. A near-field transducer (NFT) is at an end of the channel waveguide and proximate to the media-facing surface. A laser including an active region has a longitudinal axis corresponding to a propagation direction of the channel waveguide. The active region includes a back facet and a front facet proximate the NFT. The front facet has a surface shape configured to suppress back reflection of the light.

Abstract: Carriers may be adapted, or configured, to allow devices received thereby to move towards and away from an interface end region. When devices are positioned proximate the interface end region of the carriers, interfaces of the devices may be presented by the carriers for operable coupling to an enclosure. When devices are positioned away from the interface end region of the carriers, interface adapters may be coupled to the interfaces of the devices, which may present a different interface for operable coupling to an enclosure.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: A recording head has a waveguide that delivers optical energy from an energy source and a write pole extending to a media-facing surface of the recording head. The recording head also has a near-field transducer coupled to receive the optical energy from the waveguide and emit surface plasmons from the media-facing surface towards a recording medium while the write pole applies a magnetic field to the recording medium. The near-field transducer has an extended portion that, as-manufactured, protrudes beyond the media-facing surface by a first distance.

Abstract: Systems and methods are disclosed for a multiple detector data channel and data detection utilizing different cost functions. For example, a digital data channel system can have multiple data detectors where each data detector implements a distinct cost function for detecting data. A cost function analyzer can then selectively choose decisions from the multiple data detectors to generate a data sequence. In some examples, a dual detector system may have one detector implement a Soft-Output Viterbi Algorithm (SOVA) cost function and another detector implement a peak detection algorithm. Further, in some embodiments, the cost function analyzer can implement multiple selection criteria to determine which decisions to include in a data sequence from the multiple data detectors.

Abstract: A background operation is internally triggered by firmware of a disk drive. During a training phase defined by a first time period, access latency of host commands is monitored during rotational position sorting command selection. During a sorting phase after the training phase, a sorting threshold is defined based on the access latencies measured during the training phase. The background command is selected for execution in the sorting phase if the seek and rotational latency is less than the sorting threshold.

Abstract: A method includes accessing a first top level entry of a first table of the base volume, the first top level entry having at least a first bottom level entry. The method also includes receiving a first request for a metadata snapshot of the base volume, including the first bottom level entry. The method also includes generating a second top level entry of the first table, the second top level entry configured to point to the at least first bottom level entry of the first table, and the second top level entry configured to operate as a first snapshot of the first table including the at least first bottom level entry.

Abstract: Systems and methods for limiting performance variation in a storage device are described. Storage devices receive work requests to perform one or more operations from other computing devices, such as a host computing device. Completing the work requests may take a response time. In some embodiments, if the response time of executing the work request exceeds a threshold, the storage device may assign additional computing resources to complete the work request.

Abstract: Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.

Abstract: A multi-port data storage device to at least provide port-to-port communication between nodes. The multi-port storage device includes a first port, a second port and a bridge. The first port can be operatively coupled to a first node of a plurality of nodes. The second port can be operatively coupled to a second node of the plurality of nodes. The bridge can receive one or more data packets via the first or second ports to be transmitted to one of the plurality of nodes and to transmit one or more received data packets to another multi-port data storage device, to the first node, or to the second node.

Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.

Abstract: Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.