Abstract: Implementations described and claimed herein provide a method and system for detecting slow storage drives. In one implementation, the method includes dynamically creating a storage drive peer group including a plurality of storage drives, comparing performance statistics of the storage drives in the storage drive peer group, selecting an outlier storage drive of the storage drive peer group based on the comparison of the performance statistics, passively monitoring response times of the storage drives in the storage drive peer group, comparing average response times of the storage drives in the storage drive peer group, flagging an outlier storage drive of the storage drive peer group with an outlier storage drive designation responsive to comparison of the average response times, actively measuring workload metrics of the outlier storage drive, comparing workload metrics data of the outlier storage drive to workload metrics reference data, and performing a remedial action.

Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.

Abstract: A virtual solid state storage system is provided with solid state storage error emulation. An exemplary apparatus comprises a virtual solid state storage device configured to emulate a solid state storage device. The virtual solid state storage device comprises an interface that communicates with a solid state storage controller; an address translation module that translates memory addresses from a solid state storage-based memory space to a second memory space of a second memory device; and a non-solid state storage memory controller that communicates with the second memory device; and an error module to emulate solid state storage errors for testing error handling functions of the solid state storage controller for predefined error types of the solid state storage memory device by: (i) flipping bits sent to and/or read from the second memory device; and/or (ii) changing a status response sent to the solid state storage controller.

Abstract: NAND flash storage devices and methods are provided that use a non-NAND cache to store write data until a substantially complete storage unit is available. An exemplary solid state storage device comprises a NAND flash memory device; a non-NAND cache; and a controller configured to obtain write data from a remote host for storage in the NAND flash memory device; store the write data in the non-NAND cache; and transfer the write data from the non-NAND cache to the NAND flash memory device when a predefined storage criterion is satisfied. The predefined storage criterion comprises, for example, a storage unit of the write data stored in the non-NAND cache, where the storage unit comprises a block of data erased in a single garbage collection cycle. The predefined storage criterion is optionally established to reduce open block degradation in NAND flash memory devices.

Abstract: Systems and methods are disclosed for host assisted error recovery at a data storage device. In an example embodiment, an apparatus comprises a data storage drive including an interface to communicate with a host device, a nonvolatile solid state memory, and a processor. The processor is configured to calculate parity data based on a plurality of pages from the nonvolatile solid state memory, and provide, in response to a request for the parity data received from the host device via the interface, the parity data to the host device with an indication to store the parity data to a nonvolatile storage medium.

Abstract: Apparatus and method for managing data. A host device is coupled to multiple hybrid data storage devices each having a primary non-volatile memory (NVM), a secondary NVM, a top level controller and a secondary controller. During a normal I/O processing mode, host access commands are serviced by the top level controllers to direct transfers with the respective primary and secondary NVMs. During a front end I/O processing mode, the host device forms a consolidated, distributed memory space in which data are separately stored to the secondary NVMs by the host device. The primary NVM may be rotatable recording media and the secondary NVM may be flash memory. The secondary NVM may be in the form of removable SSD cards that plug into the storage devices to support replacement and performance upgrades, as well as allowing transitions between cold and hot data storage modes in a single system.

Abstract: A recording head has a first magnetic writer and a second magnetic writer offset from the first magnetic writer in a downtrack and crosstrack direction. The recording head has leads configured to deliver respective first and second write and/or laser currents to the first and second writers. The first and second write and/or laser currents enable the first and second writers to simultaneously write to adjacent tracks of a magnetic disk.

Abstract: A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. The given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.

Abstract: An apparatus may comprise a circuit configured to receive first underlying data corresponding to a first signal and receive a second signal corresponding to second underlying data. The circuit may determine an interference component signal based on the first underlying data corresponding to the first signal and a first channel pulse response shape for the first signal, determine estimated decisions corresponding to the second signal based on the second signal, and determine an estimated signal based on the estimated decisions corresponding to the second signal and a second channel pulse response shape for the second signal. The circuit may then generate a remaining signal based on the estimated signal and the second signal, generate an error signal based on the interference component signal and the remaining signal, and adapt one or more parameters of the first channel pulse response shape based on the error signal.

Abstract: An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

Abstract: Certain exemplary aspects of the present disclosure are directed towards apparatuses and methods which autonomously decontaminate parts. Parts to be cleaned are identified, and based on the identification of the part, a part specific cleaning program is initiated. During the cleaning, the part is manipulated about a gas supply in such a way that the drag force on the contamination particles attached to the part exceeds the contamination particles' surface adhesion force and accordingly is removed from the surface of the part. The removed contamination is then evacuated from the atmospheric environment near the part by a low pressure zone of a second gaseous material near the part.

Abstract: Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.

Abstract: Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).

Abstract: A computing system can be arranged to generate a range of different frequencies with at least one oscillator of a clock module prior to providing a first clock frequency to a controller with a channel selector of the clock module in response to a dither control circuit. A system operation may be executed with the controller before the first clock frequency is changed to a second clock frequency during the execution of the system operation as directed by the dither control circuit. The second clock frequency can be chosen from the range of different frequencies. The computing system may return to the first clock frequency at the conclusion of the execution of the system operation.

Abstract: Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with reference cells of a plurality of groups of pages of a non-volatile memory (NVM), and predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages. The predicting of values for an optimal read threshold voltage may be based at least on the selected retention drift predictor scheme and the read retention drift history.

Abstract: A disk drive including a disk drive base having a lower portion and a base post extending upwardly from the lower portion, a rotatable spindle attached to the disk drive base, and a head actuator pivotally attached to the disk drive base. The head actuator includes an actuator body having a bore therein, and an actuator pivot bearing disposed at least partially within the bore, the actuator pivot bearing having a cover attachment member extending at least partially into a distal end of the base post. An upper portion of the pivot shaft includes an annular groove and a lower portion of the pivot shaft includes an annular recess.

Abstract: Security of computers, data storage devices, and servers can be improved with a multiple key access system. In some embodiments, a local key management device can be a locally (or virtually) located data storage device such as a HDD or SDD. The key management device may be part of a computer or server system and can have a first secure area protected by a cryptographic module (e.g. hardware integrated circuit). The first secure area can store a key to access a second secure area, which may function as a local key management server (LKMS) and store access information to authenticate another data storage device coupled to the computer. For example, the LKMS may store an access key to provide the computer with access to another data storage device.

Abstract: A disk drive assembly including a spindle motor including a hub and a central axis, at least one disk disk having a central opening positioned on the hub and concentric about the central axis, an annular ring member concentric about the central axis, wherein a first portion of the annular ring member is in contact with an outer surface of a top disk of the disk stack, and a disk clamp ring screw adjacent to and in contact with a second portion of the annular ring member, wherein the disk clamp ring screw provides a clamping force to at least partially compress the annular ring member toward the top disk of the disk stack.

Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A top level controller circuit directs a first portion of the received access commands to the HDD controller circuit and a second portion of the received access commands to the SSD controller circuit. The top level controller circuit performs an embedded queuing operation to forward internally generated data cleaning commands to an HDD command queue to write data previously transferred from the host device to the solid state memory to the rotatable storage media concurrently while least one of the first portion of the access commands is pending in the HDD command queue.

Abstract: A data storage system can have multiple parity redundancy with a plurality of data storage units arranged into logical rows and logical columns. A controller connected to the plurality of data storage units can orchestrate the logical rows storing striped data having at least one rotational parity value and each logical column storing striped data with a static parity value. The static parity value of each logical column may be computed from the at least one rotational parity value of at least one logical row as directed by the controller.