Abstract: A source and a drain of a field-effect transistor are formed so as to fulfill a specified physical relationship to upper and lower gates thereof and thereby parasitic capacitance that hampers its high-speed operation is minimized. The filed-effect transistor includes a second support substrate, a lower gate that is embedded in an insulator formed on the second support substrate, an insulating layer formed on the lower gate, a semiconductor layer formed on the insulating layer, an insulating layer formed on the semiconductor layer, an upper gate formed on the insulating layer, as well as a source electrode, a drain electrode, an upper gate electrode, and a lower gate electrode all of which are isolated from one another by the insulating layer.