Patents Assigned to Seeq Technology, Inc.
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Patent number: 5912924Abstract: A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.Type: GrantFiled: August 15, 1996Date of Patent: June 15, 1999Assignee: SEEQ Technology, Inc.Inventors: Stephen F. Dreyer, Lee-Chung Yiu, Robert X. Jin
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Patent number: 5898678Abstract: In a 100BASE-T4 protocol network, the "carrier.sub.-- status" signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.Type: GrantFiled: September 25, 1996Date of Patent: April 27, 1999Assignee: Seeq Technology, Inc.Inventors: Robert X. Jin, Eric T. West, Kathy L. Peng, Stephen F. Dreyer
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Patent number: 5790888Abstract: A multiple-register-access-capable device includes a serial port coupled to a plurality of registers. The multiple-register-access-capable device is controlled by a state machine. Information in one of the registers identifies whether the device is in a single-register or multiple-register mode. The state machine which controls the device operates in a single-register mode if the bit is disabled and operates in a multiple-register mode if the bit is enabled. In single-register mode, the device operates in a manner known in the prior art whereby a single register is identified for reading or writing and data is then either written into the register or read out from the register in response to a write or read request. In multiple register mode, data is written into or read out from all registers in a selected group of registers in the device in response to the write or read request.Type: GrantFiled: August 12, 1996Date of Patent: August 4, 1998Assignee: SEEQ Technology, Inc.Inventors: Stephen F. Dreyer, Rong-Hui Hu
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Patent number: 5777488Abstract: The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.Type: GrantFiled: April 19, 1996Date of Patent: July 7, 1998Assignee: Seeq Technology, Inc.Inventors: Stephen F. Dryer, Rong-Hui Hu
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Patent number: 5606295Abstract: A one pin on-chip crystal oscillator circuit and a method of operating that oscillator are provided. The oscillator makes use of the gate-source capacitance of a MOS transistor to provide capacitance which would otherwise need to be provided by one of two oscillator capacitors. The MOS transistor is provided with a floating well by coupling its body to its source, so that the gate-source capacitance does not change substantially when the transistor is turned off. In another aspect of the invention, the MOS transistor is provided with a floating well using a parallel combination of MOS transistor elements, so as to minimize the coupling resistance of the MOS transistor to other elements of the circuit.Type: GrantFiled: April 17, 1996Date of Patent: February 25, 1997Assignee: SEEQ Technology, Inc.Inventors: Harlan H. Ohara, Lee C. Yiu
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Patent number: 5504738Abstract: A downward compatible full-duplex 10Base-T ethernet transceiver associated with both the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and detector circuitry for detecting transmission of such a signal from the transceiver with which it is communicating across the twisted pair link. The detector circuitry responds to the full-duplex-capability signal by sending a full-duplex enable signal to an ethernet controller configured according to the present invention. An ethernet controller contains circuitry responsive to the full-duplex-enable signal to disable transmission deferral in response to a carrier-sense signal generated by the transceiver. The full-duplex-capability indicator portion may comprise an extra pulse following an Nth link-integrity pulse after a delay of between about 2-7 .mu.sec.Type: GrantFiled: April 15, 1994Date of Patent: April 2, 1996Assignee: Seeq Technology Inc.Inventors: Namakkal S. Sambamurthy, Woo-Ping Lai, John P. VanGilder
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Patent number: 4855955Abstract: The memory cell of the present invention is a three transistor cell, including two floating gate MOS transistors connected in series with a select transistor. The source of the first memory cell floating gate memory transistor is connected to a source of a first potential. Its gate is connected to a first sense line. Its drain is connected to the source of the second memory cell floating gate transistor. The gate of the second memory cell floating gate transistor is connected to a second sense line. The drain of the second memory cell floating gate transistor is connected to the source of a select transistor. The gate of the select transistor is connected to a word line. The source of the select transistor is connected to a bit line.A plurality of memory cells may be connected together as a byte, and may be placed in an array. The gates of the select transistors are connected together.Type: GrantFiled: April 8, 1988Date of Patent: August 8, 1989Assignee: Seeq Technology, Inc.Inventor: Dumitru G. Cioaca
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Patent number: 4822750Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.Type: GrantFiled: July 16, 1987Date of Patent: April 18, 1989Assignee: Seeq Technology, Inc.Inventors: Gust Perlegos, Tsung-Ching Wu
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Patent number: 4785424Abstract: An apparatus for page mode programming of a memory cell with false loading protection is disclosed. The apparatus discharges any residual voltage left on the bit line after a read operation to prevent this voltage from being erroneously loaded into temporary storage apparatus associated with the bit line. In a preferred embodiment, two transistors are placed in series between the bit line and the array V.sub.ss line. A first transistor is controlled by a signal indicating that information is to be loaded into the temporary storage apparatus. The second transistor is controlled by a signal indicating that no memory cell associated with the bit line has been selected for programming.Type: GrantFiled: May 27, 1986Date of Patent: November 15, 1988Assignee: Seeq Technology, Inc.Inventors: Tien-Ler Lin, Dumitru Cioaca
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Patent number: 4783766Abstract: An electrically programmable, electrically erasable semiconductor memory apparatus for storing information in which the equivalent of a floating gate memory device and a select transistor device are combined in a single device cell is disclosed. A single control gate both controls a select transistor and is used in programming the floating gate.Type: GrantFiled: May 30, 1986Date of Patent: November 8, 1988Assignee: SEEQ Technology, Inc.Inventors: Gheorghe Samachisa, George Smarandoiu, Chien-Sheng Su, Ting-Wah Wong
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Patent number: 4768169Abstract: A memory array is organized into rows and columns of memory cells, each cell having a configuration which passes current or blocks current depending upon the state of that cell. The array includes sense circuits to sense cell state. In a preferred embodiment of the invention, an address signal sent to the memory array activates two sets of memory cells connected to the same sense lines, and the threshold level of the sense circuits is set above the level which would be sensed for a failed bit, so that a failed bit appears as if unprogrammed or erased. Because each bit is represented by a pair of memory cells, a failed cell in a pair will not affect operation of the functioning cell in the pair or result in error.Type: GrantFiled: October 28, 1983Date of Patent: August 30, 1988Assignee: SEEQ Technology, Inc.Inventor: George Perlegos
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Patent number: 4725984Abstract: Individual CMOS floating-gate memory cells capable of storing data are arranged in an array structure and selected with horizontal and vertical access lines. Current flow through the array cells is measured, amplified, and then compared with an unprogrammed cell using the sense amplifier of the present invention. The sense amplifier tolerates increased variation in the characteristics of programmed or unprogrammed cells and therefore increases the manufacturing yields of the arrays. It additionally achieves fast accessing and sensing of the stored data.Type: GrantFiled: February 21, 1984Date of Patent: February 16, 1988Assignee: Seeq Technology, Inc.Inventors: William W. Ip, Gust Perlegos
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Patent number: 4701776Abstract: A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.Type: GrantFiled: December 1, 1986Date of Patent: October 20, 1987Assignee: Seeq Technology, Inc.Inventors: Gust Perlegos, Tsung-Ching Wu
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Patent number: 4673829Abstract: A charge pump for providing programming voltages to the word lines of a semiconductor memory array is disclosed. The charge pump, configured as a combination of enhancement and native MOS transistors, prevents DC current from flowing from the source of the programming voltage to ground through unselected word lines, and thereby permits the design of semiconductor programmable memory arrays having on-chip programming voltage generation, allowing for design of semiconductor programmable memory arrays which operate from a single voltage power supply.Type: GrantFiled: February 8, 1985Date of Patent: June 16, 1987Assignee: Seeq Technology, Inc.Inventor: Anil Gupta
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Patent number: 4617651Abstract: A semiconductor memory circuit having primary and redundant arrays with the capability of substituting the redundant arrays for defective primary arrays by address location.Type: GrantFiled: February 22, 1984Date of Patent: October 14, 1986Assignee: Seeq Technology, Inc.Inventors: William W. Ip, Gust Perlegos
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Patent number: 4612640Abstract: An on-chip checking and correction circuit extends the program/erase endurance of a semi-conductor memory array and catches data retention failures in individual memory cells of the array. For each data byte in the memory array, four parity bits are computed using a modified Hamming Code and stored in additional bit cells associated with that data byte. During read and write operations, check bits are calculated using the same Hamming Code and used to correct single-bit errors; error checking and correction is repeated if necessary up to a predetermined number of tries.Type: GrantFiled: February 21, 1984Date of Patent: September 16, 1986Assignee: Seeq Technology, Inc.Inventors: Sanjay Mehrotra, Gust Perlegos
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Patent number: 4558344Abstract: An MOS memory cell (44) including an electrically-programmable and electrically-erasable storage device (46) fabricated on a semiconductor substrate (50) is disclosed. The storage device (46) is divided into sensing and programming sections (90, 92), each of which sections comprises vertically-aligned floating gate and program gate portions (62L, 62R, 72L, 72R) respectively formed from first and second electrically-conductive strips (62, 72). A tunneling region (60) is formed in the substrate (50) beneath the floating gate portion (62R) of the storage device programming section (92) and a thin tunnel dielectric (70) is interposed between the tunneling region (60) and the programming section floating gate portion (62R to facilitate tunneling of charge carriers therebetween. First and second source/drain regions (94, 96) physically isolated from the tunneling region (60) are established in the substrate (50) in alignment with the sensing section floating gate and program gate portions (62L, 72L).Type: GrantFiled: January 29, 1982Date of Patent: December 10, 1985Assignee: Seeq Technology, Inc.Inventor: George Perlegos
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Patent number: 4546454Abstract: A non-volatile memory cell circuit is used to replace a polysilicon fuse as an enabling element for a redundant row or column of memory cells in a semiconductor memory array. The fuse is divided into read and program sections, allowing a large device to be used for reading and a small device to be used for programming, thus permitting programming of all fuses in a redundant row simultaneously with minimal current consumption. The circuit may be embodied as a five-device or a four-device configuration.Type: GrantFiled: November 5, 1982Date of Patent: October 8, 1985Assignee: Seeq Technology, Inc.Inventors: Anil Gupta, George Perlegos
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Patent number: 4538245Abstract: A semiconductor memory having back-up storage devices arranged along redundant word lines to replace defective storage devices located in the primary array of the memory. The memory includes a redundant decoder for enabling the redundant word lines in response to a selected address and a redundancy disable circuit for generating a signal indicative of redundant word line use.Type: GrantFiled: April 12, 1982Date of Patent: August 27, 1985Assignee: SEEQ Technology, Inc.Inventors: George Smarandoiu, George Perlegos
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Patent number: 4535259Abstract: A sense amplifier (124) for use in determining the binary state of a selected storage device (4) in a semiconductor memory array (2) is disclosed. The sense amplifier (124) comprises a sensing section (150), a reference signal generator (148), and an inverting amplifier section (152). A relatively small current transistor (164) connected between a source of operating potential (158) and a voltage node (162) in the sensing section (150) supplies read currents to the selected storage device (4) via an enabled bit line (8) in the array (2). A second transistor (168) of relatively large size connected to the voltage node (162) in parallel with the current transistor (164) operates to rapidly raise the potential on the bit line (8) when the bit line (8) is first enabled. A third transistor (166) also of relatively large size connected between the voltage node (162) and the bit line (8) serves as a transfer gate for read currents. The reference signal generator (148) feeds a reference potential V.sub.Type: GrantFiled: June 18, 1982Date of Patent: August 13, 1985Assignee: Seeq Technology, Inc.Inventors: George Smarandoiu, George Perlegos