Patents Assigned to Sehyang Industrial Co., Ltd.
  • Publication number: 20130242461
    Abstract: A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer including adjusting and setting a distance between a single shadow mask installed to a mask set to be rotated and revolved and having a plurality of slits, positioning a dielectric layer deposition source to be perpendicular to the single shadow mask and a conductor layer deposition source to be oblique to the single shadow mask, and forming the dielectric layer and the conductor layer in the vacuum deposition while controlling the mask set to move along the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction).
    Type: Application
    Filed: April 30, 2013
    Publication date: September 19, 2013
    Applicant: Sehyang Industrial Co., Ltd.
    Inventor: Jae-Ho HA
  • Patent number: 8443498
    Abstract: The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: May 21, 2013
    Assignee: Sehyang Industrial Co., Ltd.
    Inventor: Jae-Ho Ha
  • Patent number: 7975371
    Abstract: The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 12, 2011
    Assignee: Sehyang Industrial Co., Ltd.
    Inventor: Jae-Ho Ha
  • Patent number: 7503696
    Abstract: A pack sealing method and device in which a slit tubular member (16) is slidably fitted around a wrapped portion of a pack (8) (a bag or envelope made of a diverse material while having a diverse size and a diverse shape) formed as a portion of the pack (8) near an opening (4) of the pack (8) is wrapped around a rod member (14), in a state in which a diverse liquid, gaseous, and solid material or object is put into the pack (8) through the opening (4). The rod member (14?) is fixedly bonded to the inner or outer surface of the pack (8) or separate from the pack (8). Where the pack (8) is a zipper pack provided with a zipper, this zipper functions as the rod member.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: March 17, 2009
    Assignee: Sehyang Industrial Co., Ltd.
    Inventors: Jae-Ho Ha, Seung-Taek Lee