Patents Assigned to Seiko Epso Corporation
  • Publication number: 20040036826
    Abstract: The invention provides a reflection type liquid crystal device, and a projection type display and electronic equipment in which display defects caused by disclination are reduced, minimized or prevented from being produced for a highly fine liquid crystal display with a space between pixels made to be narrow to make it possible to provide a high-contrast and bright display. A liquid crystal device includes a liquid crystal layer sandwiched between a first substrate and a second substrate, and a first electrode and a second electrode formed on a face of the above-described second substrate on a side of the above-described liquid crystal layer. The above-described first electrode and the above-described second electrode are formed so that an electric field substantially parallel to the surface of the substrate with respect to the above-described liquid crystal layer can be applied thereto.
    Type: Application
    Filed: August 29, 2003
    Publication date: February 26, 2004
    Applicant: Seiko Epso Corporation
    Inventors: Tsuyoshi Maeda, Kinya Ozawa, Osamu Okumura, Eiji Okamoto, Hirotaka Kawata, Toshiharu Matsushima, Takumi Seki, Kimitaka Kamijo
  • Patent number: 5872027
    Abstract: A master slice type gate array has a plurality of block areas. Each block area includes a plurality of basic cells arranged in a matrix. Different block areas have transistors with different channel widths. Within each of the block areas, a plurality of basic cells are connected to one another through a wiring layer to form function cells. First layer wirings for the function cells are completed within an area between rows of power source wirings Vdd and Vss of the first layer in the transverse direction. Contacts for connecting the sources and drains of P- and N-channel type MOS transistors to the first layer wirings are arranged in rows. Even if the channel widths are changed, the position of the contacts for forming the function cells and the wiring pattern remain unchanged for every block. Therefore, the master slice type gate array can be optimized for various performance parameters such as speed, integration, power consumption and other factors.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: February 16, 1999
    Assignee: Seiko Epso Corporation
    Inventor: Masao Mizuno