Patents Assigned to SEIKO EPSON COPRORATION
  • Patent number: 10852599
    Abstract: A chip serving as an individual substrate includes an internal circuit, and an external coupling terminal serving as a first coupling terminal arranged on a first side of the chip. One end side of the external coupling terminal is electrically coupled, via a first electrostatic protection circuit, to a guard line serving as a first common wiring extending along the first side, and another end side is electrically coupled to the internal circuit via a coupling wiring serving as a first coupling wiring. An internal circuit side of the coupling wiring is electrically coupled, via a second electrostatic protection circuit, to a guard line serving as a second common wiring extending along a second side intersecting the first side.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: December 1, 2020
    Assignee: SEIKO EPSON COPRORATION
    Inventor: Masahito Yoshii