Patents Assigned to Seiko Instruments Inc.
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Patent number: 8920022Abstract: Provision of a waterproof device capable of improving waterproof property in a push-in operation portion formed by including an extensible member, a holding member and an operation shaft. A wrist watch (portable device) 11 includes an outer case (device outer housing) 12, an extensible member 32 with waterproof property, a holding member 41 attached to the case 12 and an operation shaft 51. The case 12 includes a seating portion 29 and a hole 30. The extensible member 32 includes a cylindrical portion 33 which can be extended/retracted in an axial direction, closing one end as well as opening the other end, and inserted into the hole 30, and a flange 35 projecting integrally from an outer periphery of the other end portion of the cylindrical portion and seated on the seating portion 29.Type: GrantFiled: February 17, 2014Date of Patent: December 30, 2014Assignee: Seiko Instruments Inc.Inventors: Masahiro Ishida, Masataka Hayashi
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Patent number: 8922188Abstract: Provided are a low pass filter circuit having a small output voltage shift caused by a substrate leakage current at high temperature, and a voltage regulator using the low pass filter circuit, which has a small output voltage shift at high temperature. In a low pass filter circuit using a PMOS transistor as a resistive element, a back gate terminal of the PMOS transistor is set to have a higher voltage than a source of the PMOS transistor. Further, in a voltage regulator incorporating the low pass filter circuit to an output of a reference voltage circuit, the voltage of the back gate terminal of the PMOS transistor which is higher than that of the source thereof is generated by the reference voltage circuit.Type: GrantFiled: February 27, 2013Date of Patent: December 30, 2014Assignee: Seiko Instruments Inc.Inventor: Kaoru Sakaguchi
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Patent number: 8917478Abstract: A bearing device has two or more bearings each having an inner ring and an outer ring disposed on the same axis. A ring-shaped holder is disposed between the inner ring and the outer ring and has circumferentially spaced-apart rolling element pockets with a concave grease pocket between each two adjacent rolling element pockets. Rolling elements are disposed in a rollable manner in respective ones of the rolling element pockets and a grease is stored in the grease pockets, the grease serving as a lubricant of the rolling element. The grease consists of at least a base oil comprised of aromatic carbon and a thickener, the content of the aromatic hydrocarbon being 70 weight % or more of the grease.Type: GrantFiled: September 30, 2013Date of Patent: December 23, 2014Assignee: Seiko Instruments Inc.Inventors: Kenji Suzuki, Tsuyoshi Kashiwada, Robert Gordon Smith, Virat Sornsiri
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Patent number: 8916289Abstract: An electrochemical element comprises a container and a sealing plate for sealing an opening of the container. The container is sealed with the sealing plate by welding a portion of the brazing material on the sealing plate and a portion of the metal film of the container which make contact with each other together in a state where a first electrode active material, a separator, a second electrode active material and an electrolyte are contained in the container. An electricity collector sheet is electrically connected to the first electrode active material or the second electrode active material, whichever is closer to the opening of the container. At least a portion of the electricity collector sheet extends to the end portion of the container so that the container and the sealing plate are welded together with the extending portion of the electricity collector sheet in between.Type: GrantFiled: February 25, 2008Date of Patent: December 23, 2014Assignee: Seiko Instruments Inc.Inventors: Shunji Watanabe, Hideharu Onodera, Ryo Sato
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Publication number: 20140368178Abstract: Provided is a voltage regulator that uses an NMOS transistor as an output transistor and is low in power consumption. The voltage regulator includes an output transistor formed of an NMOS transistor, and a voltage drop circuit connected between a drain of the output transistor and a power supply.Type: ApplicationFiled: June 3, 2014Publication date: December 18, 2014Applicant: Seiko Instruments Inc.Inventor: Osamu UEHARA
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Publication number: 20140361746Abstract: The present invention provides a charge/discharge control circuit and a battery device capable of detecting an intermediate terminal disconnection without causing the balance between battery voltages to collapse and shortening the service life of the battery device. A charge/discharge control circuit which controls charging/discharging of a plurality of secondary batteries connected in series is equipped with intermediate terminal disconnection detecting circuits each of which is provided between a positive electrode terminal and a negative electrode terminal of each secondary battery and detects an intermediate terminal disconnection of each intermediate terminal by intermittently equal detection currents.Type: ApplicationFiled: May 28, 2014Publication date: December 11, 2014Applicant: Seiko Instruments Inc.Inventor: Hiroshi SAITO
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Patent number: 8905805Abstract: A U-shaped groove and a V-shaped groove are formed onto a cladding disposed on a substrate, a core and a metal structure are formed inside the grooves, respectively, and then the substrate surface is planarized. Further, after a cladding is formed again, the substrate is cut and the cut surface is polished such that the metal structure inside the V-shaped groove has a predetermined thickness, thereby forming a scattering body.Type: GrantFiled: February 9, 2012Date of Patent: December 9, 2014Assignee: Seiko Instruments Inc.Inventors: Yoko Shinohara, Norio Chiba, Manabu Oumi, Masakazu Hirata, Sachiko Tanabe, Yoshikazu Tanaka
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Patent number: 8907717Abstract: The light receiving circuit includes: a photoelectric conversion element for causing a current corresponding to an amount of incident light to flow; a MOS transistor including a source connected to the photoelectric conversion element and a drain connected to a node, for causing the current of the photoelectric conversion element to flow to the node while maintaining a voltage of the source to a first voltage; a reset circuit for causing a current to flow from the node to a GND terminal so that a voltage of the node becomes a second voltage lower than the first voltage; a control circuit for outputting a reset signal to the reset circuit; and a voltage increase detection circuit for detecting a fluctuation in the voltage of the node and outputting a detection result.Type: GrantFiled: March 14, 2014Date of Patent: December 9, 2014Assignee: Seiko Instruments Inc.Inventor: Fumiyasu Utsunomiya
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Patent number: 8907443Abstract: In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection.Type: GrantFiled: August 14, 2008Date of Patent: December 9, 2014Assignee: Seiko Instruments Inc.Inventor: Hiroaki Takasu
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Publication number: 20140354249Abstract: Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.Type: ApplicationFiled: May 27, 2014Publication date: December 4, 2014Applicant: Seiko Instruments Inc.Inventors: Tadashi KUROZO, Tomoyuki YOKOYAMA
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Patent number: 8901966Abstract: Provided is a sensor circuit which can amplify a sensor signal at high speed and with a high amplification factor without increasing the current consumption. The sensor circuit includes a primary amplifier for amplifying in advance a differential output signal which is a current signal of a sensor element, a secondary amplifier for amplifying the amplified differential output signal, a constant voltage generating circuit for maintaining a sensor element driving current to be constant, and a feedback circuit for feeding back a feedback signal to adjust an amplification factor. Most of the currents which pass through the primary amplifier are bias currents of the sensor element.Type: GrantFiled: February 12, 2014Date of Patent: December 2, 2014Assignee: Seiko Instruments Inc.Inventor: Kiyoshi Yoshikawa
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Patent number: 8902645Abstract: Provided is a semiconductor memory circuit excellent in long-term reliability and reading characteristics and having low current consumption. The semiconductor memory circuit includes: a first inverter; a first non-volatile memory, which is electrically writable; a second inverter; and a second non-volatile memory, the first inverter having an output connected to a source of the first non-volatile memory, the first non-volatile memory having a drain connected to an input of the second inverter, the second inverter having an output connected to a source of the second non-volatile memory, the second non-volatile memory having a drain connected to an input of the first inverter, the drain of the second non-volatile memory serving as an output of the semiconductor memory circuit.Type: GrantFiled: September 23, 2013Date of Patent: December 2, 2014Assignee: Seiko Instruments Inc.Inventor: Kazuhiro Tsumura
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Patent number: 8898875Abstract: Providing a method for manufacturing a package capable of achieving reliable anodic bonding between the bonding material and a base board wafer even when the bonding material having a large resistance value is used. Providing a method for manufacturing a package by anodically bonding a bonding material, which is fixed in advance to an inner surface of a lid board wafer made of an insulator, to an inner surface of a base board wafer made of an insulator, the method including an anodic bonding step where an auxiliary bonding material serving as an anode is disposed on an outer surface of the lid board wafer, a cathode is disposed on an outer surface of the base board wafer, and a voltage is applied between the auxiliary bonding material and the cathode, wherein the auxiliary bonding material is made of a material that causes an anodic bonding reaction between the auxiliary bonding material and the lid board wafer in the anodic bonding step.Type: GrantFiled: August 25, 2010Date of Patent: December 2, 2014Assignee: Seiko Instruments Inc.Inventor: Takeshi Sugiyama
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Publication number: 20140347022Abstract: Provided is a voltage regulator capable of accurately adjusting a tail current of a differential amplifier circuit without adding a test terminal. The voltage regulator includes: a constant current circuit for causing the tail current of the differential amplifier circuit to flow; a protection circuit; a current output circuit for outputting a current of the constant current circuit to a test terminal for measuring characteristics of the protection circuit; a switch circuit for stopping a function of the protection circuit; and a fuse provided between the test terminal and the current output circuit.Type: ApplicationFiled: May 8, 2014Publication date: November 27, 2014Applicant: Seiko Instruments Inc.Inventors: Akihito YAHAGI, Takashi IMURA
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Patent number: 8896268Abstract: There is provided a charge/discharge control circuit and a battery assembly including an accurate overcurrent protecting circuit with low consumption current characteristics. The charge/discharge control circuit comprises a current protecting circuit including: a reference voltage circuit having a reference transistor for detecting overcurrent flowing through a control transistor to turn it on, and a constant current circuit; and a comparison circuit for comparing voltage on the reference voltage circuit with voltage generated by overcurrent flowing through the control transistor, wherein when no overcurrent flows, the electric current flowing through the reference voltage circuit is interrupted to reduce power consumption.Type: GrantFiled: February 24, 2012Date of Patent: November 25, 2014Assignee: Seiko Instruments Inc.Inventors: Atsushi Sakurai, Toshiyuki Koike, Satoshi Abe
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Patent number: 8897852Abstract: A biological information detection device has a device main body and a biological signal detection portion formed integrally with the device main body. The biological signal detection portion has at least one electrode for contacting a biological surface of a human body. A fixing portion has an elastic strap and is configured to mount the device main body and the biological signal detection portion to the human body without the device main body and the biological signal detection portion being directly attached to the elastic strap. The fixing portion covers the device main body and the biological signal detection portion with the electrode being disposed in contact with the biological surface of the human body when the device main body and the biological signal detection portion are mounted to the human body.Type: GrantFiled: September 27, 2012Date of Patent: November 25, 2014Assignee: Seiko Instruments Inc.Inventors: Teruo Kato, Dai Terasawa, Hideki Okuda
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Patent number: 8896277Abstract: Provided is a voltage regulator including a soft-start circuit having a small area and capable of suppressing an inrush current by causing a reference voltage circuit to rise gently with time. In the soft-start circuit, a capacitor is connected to an output of a reference voltage circuit driven by a constant current of a constant current circuit, and hence the soft-start circuit can raise a reference voltage gently to prevent an inrush current with a small area. After the end of a soft-start period, the constant current circuit is disconnected, and the reference voltage circuit is driven by a power source. Thus, the operation becomes stable.Type: GrantFiled: December 18, 2012Date of Patent: November 25, 2014Assignee: Seiko Instruments Inc.Inventors: Akihito Yahagi, Takashi Imura
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Patent number: 8884602Abstract: A constant current flowing through a first depletion transistor whose gate and source are connected to each other is caused to flow through a second depletion transistor having the same threshold as the first depletion transistor, to thereby generate a first voltage between a gate and a source of the second depletion transistor. The constant current of the first depletion transistor and a constant current flowing through a third depletion transistor whose gate and source are connected to each other are caused to flow through a fourth depletion transistor. A threshold of the fourth depletion transistor is the same as that of the third depletion transistor but different from that of the first depletion transistor, and hence a second voltage is generated between a gate and a source of the fourth depletion transistor. A reference voltage is generated based on a voltage difference between the first and second voltages.Type: GrantFiled: February 28, 2013Date of Patent: November 11, 2014Assignee: Seiko Instruments Inc.Inventor: Fumiyasu Utsunomiya
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Patent number: 8884594Abstract: Provided is a voltage regulator having improved overshoot characteristics. In the voltage regulator, a current limiting circuit formed of, for example, a constant current source is provided in series to an output transistor, to thereby limit an output overcurrent. Further, a voltage limiting circuit formed of, for example, a diode is provided to an output terminal, to thereby limit an output voltage.Type: GrantFiled: February 13, 2012Date of Patent: November 11, 2014Assignee: Seiko Instruments Inc.Inventor: Masakazu Sugiura
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Patent number: D719553Type: GrantFiled: July 29, 2013Date of Patent: December 16, 2014Assignee: Seiko Instruments Inc.Inventor: Naohiko Noto