Patents Assigned to Seiko Instruments
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Patent number: 9172332Abstract: Provided is an operational amplifier circuit having a high tolerance for clock phase difference fluctuations. An FIR filter is used to add an input signal of the FIR filter to a signal obtained by delaying the input signal of the FIR filter. In this manner, chopper noise can be removed. Thus, the operational amplifier circuit may have a high tolerance for clock phase difference fluctuations regardless of the phase difference between clocks for controlling a chopper circuit and the FIR filter.Type: GrantFiled: January 29, 2014Date of Patent: October 27, 2015Assignee: Seiko Instruments Inc.Inventor: Tsutomu Tomioka
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Patent number: 9110487Abstract: Provided is a voltage regulator including an overcurrent protection circuit, which does not need a test circuit. The voltage regulator has a configuration in which a reference voltage circuit includes an element that determines a reference voltage and an overcurrent protection circuit includes an element that determines a maximum output current, the element of the reference voltage circuit and the element of the overcurrent protection circuit having the same characteristics. Accordingly, there is a correlation between an output voltage before trimming and the maximum output current for overcurrent protection. Thus, a maximum output current before trimming can be estimated without performing evaluation by a test circuit.Type: GrantFiled: May 2, 2012Date of Patent: August 18, 2015Assignee: Seiko Instruments Inc.Inventors: Kaoru Sakaguchi, Takashi Imura
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Patent number: 9063013Abstract: Provide is an infrared detector that has a simple configuration, has a high amplification factor, and is configured to operate at low voltage. An NMOS transistor at an output stage of a pyroelectric infrared detection element serves as a common source amplifier circuit in which a source is connected to GND via a resistor and a capacitor that are connected in parallel.Type: GrantFiled: August 27, 2014Date of Patent: June 23, 2015Assignee: Seiko Instruments Inc.Inventor: Fumiyasu Utsunomiya
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Patent number: 9059699Abstract: Provided is a power supply switching circuit capable of suppressing a load fluctuation such as undershoot that occurs at an output terminal at the time of power supply switching. The power supply switching circuit includes: a battery connected to the output terminal; a replica current generation circuit for generating a replica current that is proportional to a current flowing from the battery to the output terminal; a voltage regulator connected to the output terminal, the voltage regulator including a reference voltage circuit, an error amplifier circuit, an output transistor, and a voltage divider circuit; and a current mirror circuit for causing the replica current to flow through the output transistor of the voltage regulator.Type: GrantFiled: September 17, 2013Date of Patent: June 16, 2015Assignee: Seiko Instruments Inc.Inventors: Tsutomu Tomioka, Atsushi Igarashi, Masakazu Sugiura
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Patent number: 9030892Abstract: There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T2 and a static electricity convergence time T1 are set so as to keep a relation of T1<T2.Type: GrantFiled: October 30, 2012Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Kotaro Watanabe, Makoto Mitani
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Patent number: 9030180Abstract: In order to provide a switching regulator having high efficiency even under light load, the switching regulator is configured so that ON/OFF of a switching element is controlled by an output signal of an oscillation circuit having an oscillation frequency controlled by an output signal from an error amplifier. Thereby, the oscillation frequency can be suppressed under light load, thus reducing a switching loss.Type: GrantFiled: June 1, 2012Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Michiyasu Deguchi, Kenji Yoshida
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Patent number: 9028134Abstract: The present invention is to provide a portable device, such as a wrist watch, which realizes, with a simple structure, improved waterproof property against water leak associated with a push-in operation. A wrist watch (portable device) includes an outer case (device outer housing), an operation member and a holding ring. The outer case includes a holding portion in which an annular bearing surface is formed. The operation member is made of a soft material having waterproof performance. The operation member includes an annular packing portion to be seated on the bearing surface and a push-in portion integrally connected to the bearing portion, to which the push-in operation is performed from the outside of the device outer housing.Type: GrantFiled: February 19, 2014Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Hideaki Koshoji, Haruki Hiranuma
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Patent number: 9030249Abstract: There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal. The level shift circuit has a control circuit that detects when the first power supply voltage reduces below a predetermined voltage. The voltage of the output terminal of the level shift circuit is fixed to the second power supply voltage or a ground voltage according to a detection signal of the control circuit.Type: GrantFiled: February 18, 2014Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Kosuke Takada, Atsushi Igarashi
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Patent number: 9029968Abstract: An optical sensor element is mounted in a package which includes a glass substrate having a cavity, and a glass lid substrate bonded to the other substrate to close the cavity. The glass substrate with the cavity has metalized wiring patterns on front and rear surfaces thereof, and a through hole filled with metal to form a through-electrode interconnecting the wiring patterns on the front and rear surfaces. A metalized wiring pattern on the rear surface of the glass lid substrate is electrically connected to the wiring pattern on the front surface of the other substrate with an adhesive containing conductive particles. The glass lid substrate is made either of glass having a filter function or glass having a light shielding property with an opening therethrough filled with glass having a filter function.Type: GrantFiled: November 14, 2012Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Koji Tsukagoshi, Hitoshi Kamamori, Sadao Oku, Hiroyuki Fujita, Keiichiro Hayashi
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Patent number: 9013007Abstract: A depletion type MOS transistor includes a well region having a first conductivity type and formed on a semiconductor substrate, a gate insulating film formed on the well region, and a gate electrode formed on the gate insulating film. Source and drain regions having a second conductivity type different from the first conductivity type are formed on respective sides of the gate electrode and within the well region. A first low concentration impurity region has the second conductivity type and is formed below the gate insulating film between the source and drain regions and within the well region. A second low concentration impurity region has the first conductivity type and is formed below the first low concentration impurity region between the source and drain regions and within the well region.Type: GrantFiled: March 28, 2011Date of Patent: April 21, 2015Assignee: Seiko Instruments Inc.Inventor: Hirofumi Harada
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Patent number: 9006830Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad (22) to a drain of an NMOS transistor of an ESD protective circuit. The first vias (16) are formed under the pad (22) only on one side of a rectangular ring-shaped intermediate metal film (17) and on another side thereof opposed to the one side. In other words, all the first vias (16) for establishing an electrical connection to the drains are present substantially directly under the pad (22). Consequently, a surge current caused by ESD and applied to the pad (22) is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protective circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device is increased.Type: GrantFiled: October 24, 2013Date of Patent: April 14, 2015Assignee: Seiko Instruments Inc.Inventors: Takeshi Koyama, Yoshitsugu Hirose
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Patent number: 9006831Abstract: Provided is a semiconductor device having high ESD tolerance. A first via (16) is used for electrically connecting a pad to a drain of an NMOS transistor of an ESD protection circuit. The first via (16) is arranged directly above the drain and present substantially directly under the pad. Consequently, a surge current caused by ESD and applied to the pad is more likely to flow uniformly among all the drains. Then, respective channels of the NMOS transistor of the ESD protection circuit are more likely to uniformly operate, and hence the ESD tolerance of the semiconductor device increases.Type: GrantFiled: November 21, 2013Date of Patent: April 14, 2015Assignee: Seiko Instruments Inc.Inventors: Takeshi Koyama, Yoshitsugu Hirose
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Patent number: 9007026Abstract: Provided is a battery device including, in a charge/discharge protection circuit for controlling charge/discharge of a secondary battery by a single bidirectionally conductive field effect transistor, a charge/discharge control circuit with which the number of elements to be used is reduced to reduce the layout area. The charge/discharge control circuit includes a switch circuit for controlling a gate of the bidirectionally conductive field effect transistor based on an output of a control circuit for controlling the charge/discharge of the secondary battery, the switch circuit including a first terminal connected to a back gate of the bidirectionally conductive field effect transistor.Type: GrantFiled: August 12, 2011Date of Patent: April 14, 2015Assignee: Seiko Instruments Inc.Inventors: Atsushi Sakurai, Toshiyuki Koike, Kazuaki Sano, Fumihiko Maetani
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Patent number: 8998385Abstract: A thermal head including: a laminated substrate including a support substrate and an upper substrate at least one of which has a recess formed in a surface thereof; a heat generating resistor formed on a surface of the upper substrate in the laminated substrate at a position opposed to the recess; and a pair of electrode portions connected to each of both ends of a heat generating resistor, wherein the laminated substrate further includes: an intermediate metal layer sandwiched between the support substrate and the upper substrate and bonded thereto in a laminated state; and a surrounding metal layer formed of a metal material, the surrounding metal layer provided in contact with the intermediate metal layer and formed from a surface of the support substrate extending in a thickness direction thereof to a surface thereof opposite to a portion bonded to the upper substrate.Type: GrantFiled: December 20, 2012Date of Patent: April 7, 2015Assignee: Seiko Instruments Inc.Inventors: Toshimitsu Morooka, Keitaro Koroishi, Noriyoshi Shoji, Norimitsu Sanbongi
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Patent number: 9000726Abstract: Provided are a cell balance device for protecting a switch circuit from an overcurrent flow. The cell balance device includes: a plurality of electric accumulator connection terminals each connected to one of a node and two terminals of electric accumulators connected in series; a voltage hold device connection terminal connected to a voltage hold device; a plurality of first switch circuits provided between the plurality of electric accumulator connection terminals and the voltage hold device; a control circuit for controlling ON/OFF of the plurality of first switch circuits based on a synchronization signal; and an overcurrent detection circuit for detecting an overcurrent flowing through each of the plurality of first switch circuits.Type: GrantFiled: August 10, 2012Date of Patent: April 7, 2015Assignee: Seiko Instruments Inc.Inventors: Atsushi Sakurai, Hiroshi Saito
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Patent number: 9000749Abstract: Provided is a constant current circuit in which an enhancement N-channel transistor can operate in a weak-inversion state even at high temperatures. A constant current circuit includes a current mirror circuit, a constant-current generation block circuit, and an off-leak circuit, wherein the off-leak circuit is constituted by a first enhancement N-channel transistor having a gate and a source connected to an earth terminal and a drain connected to an output of the constant current circuit. This suppresses an increase in a gate-to-source voltage of the enhancement N-channel transistor which generates a constant current, thereby maintaining its operation in a weak-inversion state.Type: GrantFiled: October 25, 2012Date of Patent: April 7, 2015Assignee: Seiko Instruments Inc.Inventor: Yuji Kobayashi
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Patent number: 8994160Abstract: A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.Type: GrantFiled: September 18, 2013Date of Patent: March 31, 2015Assignee: Seiko Instruments Inc.Inventor: Noriyuki Kimura
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Patent number: 8988840Abstract: Provided is an overcharge prevention circuit for clamping a voltage value of an electric power generation unit in an overcharged state to a constant value, in which the number of elements is small and which does not consume electric power unnecessarily. The overcharge prevention circuit includes: a backflow prevention diode; a clamping transistor having a gate connected to a cathode of the backflow prevention diode, a source connected to an anode thereof, and a drain connected to an overcharge prevention switch. Upon detection of overcharge, a current is discharged via the clamping transistor and the overcharge prevention switch, thereby clamping a potential of the electric power generation unit to around a voltage of an electricity storage unit.Type: GrantFiled: September 12, 2012Date of Patent: March 24, 2015Assignee: Seiko Instruments Inc.Inventors: Makoto Mitani, Kotaro Watanabe
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Patent number: 8978217Abstract: A package manufacturing method where a base substrate and a lid substrate, at least one having a through-hole, are anodically bonded to each other using a jig having a communication-hole and arranged in a vacuum chamber to laminate the lid substrate to the base substrate and thereby form a bonded body having a plurality of cavities, each of which includes an electronic part sealed therein. The through-hole and the communication-hole are aligned with each other inside the vacuum chamber, such that gas within the cavities can escape through the through-hole and the communication-hole during bonding. A plurality of packages are formed by cutting the bonded body for every one of the plurality of cavities.Type: GrantFiled: March 26, 2012Date of Patent: March 17, 2015Assignee: Seiko Instruments Inc.Inventor: Takeshi Sugiyama
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Patent number: 8982656Abstract: Provided is a semiconductor non-volatile memory device capable of improving the accuracy of trimming by creating a written state before data is written into a non-volatile memory element. The semiconductor non-volatile memory device includes: a written data transmission circuit for transmitting written data to a non-volatile memory element; a first switch connected between the non-volatile memory element and a data output terminal; a third switch connected to an output terminal of the written data transmission circuit; and a control circuit for controlling the respective switches. When a test mode signal is input, the control circuit turns on only the first switch and the third switch so as to control the written data to be output to the data output terminal before data is written into the non-volatile memory element.Type: GrantFiled: January 30, 2014Date of Patent: March 17, 2015Assignee: Seiko Instruments Inc.Inventors: Makoto Mitani, Kotaro Watanabe