Patents Assigned to Sematech
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Patent number: 5770982Abstract: The present invention discloses a saturable reactor and a method for decoupling the interwinding capacitance from the frequency limitations of the reactor so that the equivalent electrical circuit of the saturable reactor comprises a variable inductor. The saturable reactor comprises a plurality of physically symmetrical magnetic cores with closed loop magnetic paths and a novel method of wiring a control winding and a RF winding. The present invention additionally discloses a matching network and method for matching the impedances of a RF generator to a load. The matching network comprises a matching transformer and a saturable reactor.Type: GrantFiled: October 29, 1996Date of Patent: June 23, 1998Assignee: Sematech, Inc.Inventor: James A. Moore
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Patent number: 5736457Abstract: A semiconductor process and structure is provided for use in single or dual damascene metallization processes. A thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer. Then, a second dielectric layer is deposited upon the thin metallization masking layer. The thin metallization masking layer provides an etch stop to form the bottom of the in-laid conductor grooves. In a dual damascene process, the thin metallization masking layer leaves open the via regions. Thus, the conductor grooves above the metallization masking layer and the via regions may be etched in the first and second dielectrics in one step. In a single damascene process, the thin metallization etch masking layer may cover the via regions. The etch stop and masking layer can be formed from any conductive or non-conductive materials whose chemical, mechanical, thermal and electrical properties are compatible with the process and circuit performance.Type: GrantFiled: March 5, 1997Date of Patent: April 7, 1998Assignee: SematechInventor: Bin Zhao
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Patent number: 5695810Abstract: A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.Type: GrantFiled: November 20, 1996Date of Patent: December 9, 1997Assignees: Cornell Research Foundation, Inc., Sematech, Inc., Intel CorporationInventors: Valery M. Dubin, Yosi Schacham-Diamand, Bin Zhao, Prahalad K. Vasudev, Chiu H. Ting
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Patent number: 5674787Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer.Type: GrantFiled: January 16, 1996Date of Patent: October 7, 1997Assignee: Sematech, Inc.Inventors: Bin Zhao, Prahalad K. Vasudev, Valery M. Dubin, Yosef Shacham-Diamand, Chiu H. Ting
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Patent number: 5660706Abstract: A technique for utilizing an electric field to initiate electroless deposition of a material to form layers and/or structures on a semiconductor wafer. The wafer is disposed between a positive electrode and a negative electrode and disposed so that its deposition surface faces the positive electrode. A conductive surface on the wafer is then subjected to an electroless copper deposition solution. When copper is the conductive material being deposited, positive copper ions in the solution are repelled by the positive electrode and attracted by the negatively charged wafer surface. Once physical contact is made, the copper ions dissipate their charges by accepting electrons from the conductive surface, thereby forming copper atoms on the surface. The deposited copper have the catalytic properties so that when a reductant in the solution is absorbed at the copper sites and then oxidized, additional electrons are released into the conductive surface.Type: GrantFiled: July 30, 1996Date of Patent: August 26, 1997Assignee: Sematech, Inc.Inventors: Bin Zhao, Prahalad K. Vasudev
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Patent number: 5635333Abstract: Reduction of reflection from an integrated circuit substrate during exposure of a photoresist layer on a surface such as an integrated circuit wafer is minimized by incorporating an antireflective coating between the photoresist layer and the integrated circuit substrate. The antireflective layer, after exposure and development of the photoresist layer, is preferably removed by exposing the non-masked antireflective layer to activating radiation while heating the coating to induce a solubilizing reaction in an antireflective coating and a curing reaction in an overlying photoresist mask. Thereafter, the exposed portions of the antireflective layer are removed by treatment with a suitable developer.Type: GrantFiled: December 28, 1994Date of Patent: June 3, 1997Assignees: Shipley Company, L.L.C., Sematech, Inc.Inventors: John S. Petersen, Kim R. Dean, Daniel A. Miller
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Patent number: 5614444Abstract: A method of using additives with silica-based slurries to enhance metal selectivity in polishing metallic materials utilizing a chemical-mechanical polishing (CMP) process. Additives are used with silica-based slurries to passivate a dielectric surface, such as a silicon dioxide (SiO.sub.2) surface, of a semiconductor wafer so that dielectric removal rate is reduced when CMP is applied. The additive is comprised of at least a polar component and an apolar component. The additive interacts with the surface silanol group of the SiO.sub.2 surface to inhibit particles of the silica-based slurry from interacting with hydroxyl molecules of the surface silanol group. By applying a surface passivation layer on the SiO.sub.2 surface, erosion of the SiO.sub.2 surface is reduced. However, the metallic surface is not influenced significantly by the additive, so that the selectivity of metal removal over oxide removal is enhanced.Type: GrantFiled: June 6, 1995Date of Patent: March 25, 1997Assignees: Sematech, Inc., Intel Corporation, National Semiconductor Corp., Digital Equipment Corp.Inventors: Janos Farkas, Rahul Jairath, Matt Stell, Sing-Mo Tzeng
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Patent number: 5572321Abstract: The present invention relates to a device for measuring the luminous intensity scattered by thin films of colloidal media. It is more particularly intended for submicron grain-size analysis by photon correlation, and comprises a device for measuring the luminous intensity scattered by thin films (16) of colloidal media. The invention includes a monochromatic luminous source (2); a converging optical system (4) focusing the source on the thin film to be analyzed; at least one photosensitive detector (5; 5'; 5"; 5'") detecting the light scattered or backscattered by the thin film; and a system (60, 70) for processing the signal coming from photodetector(s) (5).Type: GrantFiled: November 23, 1994Date of Patent: November 5, 1996Assignees: Institut Francais du Petrole, SematechInventors: Frank Pinier, Bill Woodley, Patrick Patin, Didier Frot
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Patent number: 5572398Abstract: A tri-polar electrostatic chuck has both positive and negative electrodes housed on a non-polarized base housing. A non-polarized guard ring surrounds the outer periphery of the chuck and enclosing the electrodes. A wafer is placed atop the chuck with its back-side cooled by a cooling gas that is piped up through the chuck. The edge of the wafer is made to reside over the guard ring, instead of over one of the polarized electrodes. The proximity of the non-polarized guard ring to the wafer edge helps to reduce the amount of plasma leakage around the edge of the wafer, resulting in less breakdown of the dielectric coating of the chuck. The positioning of the electrodes also provides for a uniform impedance across the processing surface of the wafer.Type: GrantFiled: November 14, 1994Date of Patent: November 5, 1996Assignees: Hewlett-Packard Co., International Business Machines, Corp., Sematech, Inc.Inventors: Peter Federlin, Lee Chen, D. Rex Wright
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Patent number: 5562530Abstract: A pulsed-force CMP scheme allows for the down force holding a wafer onto a pad to cycle periodically between minimum and maximum values. When the force is near its minimum value, slurry flows into the space between the wafer and the pad. When the force is near its maximum value, slurry is squeezed out allowing for the abrasive action of the pad surface to erode wafer surface features.Type: GrantFiled: August 2, 1994Date of Patent: October 8, 1996Assignee: Sematech, Inc.Inventors: Scott Runnels, L. Michael Eyman
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Patent number: 5555902Abstract: Liquid nitrogen is introduced onto a surface of a semiconductor wafer to remove submicron particles from its surface. LN.sub.2 flows across the wafer surface wherein the surface tension of the liquid collects contaminant particles and removes them off the edge of the wafer.Type: GrantFiled: May 10, 1995Date of Patent: September 17, 1996Assignee: Sematech, Inc.Inventor: Venugopal B. Menon
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Patent number: 5504328Abstract: An apparatus and method for detecting the endpoint of an etch during semiconductor fabrication is provided. The endpoint detection system utilizes a mass spectrometer having an energy source located outside the vacuum chamber of the endpoint detection system, thus providing an easily replaceable energy source. The energy source may be a light source to provide photo-ionization. The energy source may be selected based upon the gas species of the etch of which an endpoint as being detected. The energy is directed into an ionization chamber of the endpoint detection system through a transparent window.Type: GrantFiled: December 9, 1994Date of Patent: April 2, 1996Assignee: Sematech, Inc.Inventor: Douglas J. Bonser
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Patent number: 5480747Abstract: An attenuated phase shifting mask has absorbers embedded (buried) in the mask substrate, instead of on the surface of the substrate. The buried absorbers allow for controlling attenuation and phase shifting parameters. The material composition and the thickness of the absorber regions determine the amount of attenuation that is to be achieved, as well as phase shifting in some instances. In other instances, offset distances of the absorbers from the surface of the mask control the phase shift. Light scattering and diffraction is reduced or eliminated by having the absorbers below the surface of the mask. By reducing light scattering and distortion, the mask of the present invention allows for PSM lithography techniques to be extended to ranges of shorter wavelength.Type: GrantFiled: November 21, 1994Date of Patent: January 2, 1996Assignee: Sematech, Inc.Inventor: Prahalad K. Vasudev
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Patent number: 5478435Abstract: A point of use slurry dispensing system with controls for dilution, temperature and oxidizer/etchant/additive infusion. A slurry in unmixed form and a diluting agent are independently pumped to a pad on a CMP tool. Liquid heaters are used to heat the slurry and the diluting agent to a desirable temperature. The actual mixing occurs at the point of use on the pad or in a dispensing line just prior to the point of use. In some instances a third independent distribution line is used to dispense an oxidizer, etchant and/or chemical additive at or near the point of use.Type: GrantFiled: December 16, 1994Date of Patent: December 26, 1995Assignees: National Semiconductor Corp., Sematech Inc., AT&T GISInventors: James J. Murphy, Janos Farkas, Lucia C. Markert, Rahul Jairath
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Patent number: 5479340Abstract: Hotelling's T.sup.2 statistical analysis and control is used to provide multivariate analysis of components of an RF spectra for real time, in-situ control of an ongoing semiconductor process. An algorithm calculates the T.sup.2 value which is then used to generate a feedback signal, if the T.sup.2 value is out of range, to indicate an out-of-tolerance condition.Type: GrantFiled: September 20, 1993Date of Patent: December 26, 1995Assignees: Sematech, Inc., Intel CorporationInventors: Edward P. Fox, Chandru Kappuswamy
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Patent number: 5474865Abstract: A globally planarized binary optical mask has absorbers embedded (buried) in the mask substrate, instead of on the surface of the mask. Light scattering at rough vertical edges of absorbers of prior art masks are reduced or eliminated. Also, due to the buried nature of the absorbers, a triple singularity point encountered in prior art masks at the interface of three environments of quartz, absorber and air, no longer exists. The buried absorbers have an offset distance from the surface of the substrate so that with a minimum effective offset distance, defects and contaminants at the surface of the mask are no longer in the image plane, wherein alleviating a need for a pellicle to protect the mask surface. By reducing light scattering and distortion, the mask of the present invention allows for conventional optical lithography to be extended to ranges of shorter wavelength.Type: GrantFiled: November 21, 1994Date of Patent: December 12, 1995Assignee: Sematech, Inc.Inventor: Prahalad K. Vasudev
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Patent number: 5472811Abstract: A multi-layer PSM structure with multi-layer optical coating disposed between a quartz substrate and a surrounding medium, which typically is air. The multi-layer coating is comprised of a high index of refraction material overlying the quartz and a lower index of refraction material overlying the first. The multi-layer coating essentially functions as an anti-reflective coating to reduce scattering and reflection at the interface boundaries.Type: GrantFiled: April 29, 1994Date of Patent: December 5, 1995Assignees: Sematech, Inc., Motorola Inc.Inventors: Prahalad K. Vasudev, Kah K. Low
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Patent number: 5472561Abstract: A RF sensor for monitoring voltage, current and phase angle of a RF signal being coupled to a plasma reactor. Outputs from the sensor are used to calculate various properties of the plasma. These values are then utilized to characterize the process and/or used to provide feedback for in-situ control of an ongoing plasma process.Type: GrantFiled: March 27, 1995Date of Patent: December 5, 1995Assignee: Sematech, Inc.Inventors: Norman Williams, James Spain
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Patent number: 5467013Abstract: A RF sensor for monitoring voltage, current and phase angle of a RF signal being coupled to a plasma reactor. Outputs from the sensor are used to calculate various properties of the plasma. These values are then utilized to characterize the process and/or used to provide feedback for in-situ control of an ongoing plasma process.Type: GrantFiled: December 7, 1993Date of Patent: November 14, 1995Assignee: Sematech, Inc.Inventors: Norman Williams, James Spain
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Patent number: 5466991Abstract: The present invention describes a technique to control the radial profile of microwave power in an ECR plasma discharge. In order to provide for a uniform plasma density to a specimen, uniform energy absorption by the plasma is desired. By controlling the radial profile of the microwave power transmitted through the microwave window of a reactor, the profile of the transmitted energy to the plasma can be controlled in order to have uniform energy absorption by the plasma. An advantage of controlling the profile using the window transmission characteristics is that variations to the radial profile of microwave power can be made without changing the microwave coupler or reactor design.Type: GrantFiled: November 15, 1994Date of Patent: November 14, 1995Assignee: Sematech, Inc.Inventor: Lee A. Berry