Patents Assigned to Semi, Inc.
  • Patent number: 12294376
    Abstract: Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: May 6, 2025
    Assignee: Alphawave Semi, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Ayan Dutta
  • Patent number: 12199046
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: January 14, 2025
    Assignee: FARADAY SEMI, INC.
    Inventors: Martin Standing, Parviz Parto
  • Patent number: 12136676
    Abstract: Schottky diode and method for fabricating the same disclosed. The Schottky diode includes a gallium oxide layer that is a semiconductor layer doped with a first-type dopant, a cathode in ohmic contact with the gallium oxide layer and an anode having a Schottky contact metal layer in Schottky contact with the gallium oxide layer. The gallium oxide layer is in contact with an interface with the Schottky contact metal layer, contains a second-type dopant of a conductivity opposite to that of the first-type dopant, and has an interlayer which is a region where a concentration of the second-type dopant decreases as it moves away from an interface with the Schottky contact metal layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 5, 2024
    Assignee: POWERCUBE SEMI INC.
    Inventors: You Seung Rim, Tai Young Kang, Sin Su Kyoung
  • Patent number: 12119823
    Abstract: Systems and methods are disclosed for wide frequency range voltage controlled oscillators. For example, an apparatus includes a Voltage Controlled Oscillator (VCO) including a delay cell which includes first and second current sources provided in parallel with one another. The first current source is controlled by a voltage control input connected to a voltage control terminal and the second current source is controlled by a bias voltage input connected to a bias voltage terminal. The first current source provides an alternate current path in the delay cell when the second current source is off. The delay cell is operable to receive an input and produce an output using the alternate current path.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: October 15, 2024
    Assignee: Alphawave Semi, Inc.
    Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
  • Patent number: 11996770
    Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: May 28, 2024
    Assignee: FARADAY SEMI, INC.
    Inventor: Parviz Parto
  • Patent number: 11990839
    Abstract: A power converter can include first, second, third, and fourth switches, and a driver for operating the drive switches to modify an input voltage and provide an output voltage. An AC coupling capacitor can be coupled between the first and fourth switches. The first, second, third, and fourth switches can control current through two inductors. The power converter can have a fifth switch, which can provide a discharge path for discharging the first inductor, the second inductor, and/or the capacitor. Another capacitor can be between the fifth switch and ground. The power converter can provide an output voltage that is at least about ? of the input voltage. The power converter can include resonance circuitry, such as a third inductor, for soft switching the fifth switch.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: May 21, 2024
    Assignee: Faraday Semi, Inc.
    Inventors: Parviz Parto, Saurabh Anil Jayawant, Jimmy Lin
  • Patent number: 11984804
    Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: May 14, 2024
    Assignee: Active-Semi, Inc.
    Inventor: Masashi Nogawa
  • Patent number: 11940776
    Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Active-Semi, Inc.
    Inventors: Marc David Sousa, John Alexander Goodrich-Ruiz
  • Patent number: 11855534
    Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 26, 2023
    Assignee: FARADAY SEMI, INC.
    Inventors: Seungbeom Kevin Kim, Jack Walter Cornish, III, Saurabh Anil Jayawant, Parviz Parto
  • Patent number: 11727256
    Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 15, 2023
    Assignee: AIP SEMI, INC.
    Inventors: Henry Verheyen, Jianjun Wen
  • Patent number: 11652062
    Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 16, 2023
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto
  • Patent number: 11621230
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 4, 2023
    Assignee: Faraday Semi, Inc.
    Inventors: Martin Standing, Parviz Parto
  • Patent number: 11557962
    Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 17, 2023
    Assignee: Faraday Semi, Inc.
    Inventor: Parviz Parto
  • Patent number: 11385621
    Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 12, 2022
    Assignee: ACTIVE-SEMI, INC.
    Inventors: Marc David Sousa, John Alexander Goodrich-Ruiz
  • Patent number: 11385904
    Abstract: Methods and apparatus for selecting operating modes in a device are disclosed. In an embodiment, a method includes powering on a device that is configured to operate in safe and normal operating modes, detecting whether the device enters the normal operating mode within a time interval, and enabling the device to operate in the safe operating mode when the device does not enter the normal operating mode within the time interval. In an embodiment, an apparatus includes a power signal controller that powers on a device that is configured to operate in safe and normal operating modes, a state machine that detects whether the device enters the normal operating mode within a time interval, and a control signal controller that enables the device to operate in the safe operating mode when the device does not enter the normal operating mode within the time interval.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 12, 2022
    Assignee: ACTIVE-SEMI, INC.
    Inventors: Shu Ji, Chin-Ming Cheng
  • Patent number: 11381163
    Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 5, 2022
    Assignee: ACTIVE-SEMI, INC.
    Inventor: Masashi Nogawa
  • Patent number: 11309298
    Abstract: A light-emitting diode device with a driving mechanism is provided. A first light-emitting diode chip, a second light-emitting diode chip and a third light-emitting diode chip are arranged on a driver circuit chip, and respectively configured to emit red light, green light and blue light. A first contact of the light-emitting diode chip, a first contact of the second light-emitting diode chip and a first contact of the third light-emitting diode chip are respectively in direct electrical contact with a first output contact, a second output contact and a third output contact of the driver circuit chip in a flip-chip manner. A second contact of the first light-emitting diode chip, a second contact of the second light-emitting diode chip and a second contact of the third light-emitting diode chip are in direct electrical contact with a common contact of the driver circuit chip.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: April 19, 2022
    Assignee: MY-SEMI INC.
    Inventors: Cheng-Han Hsieh, Kuo-Lun Huang, Chun-Ting Kuo
  • Patent number: 11139737
    Abstract: A voltage regulator control integrated circuit includes constituent parts including an error amplifier circuit, a comparator circuit, a compensation signal generator circuit, an oscillator/one-shot circuit, a latch, and a current sense circuit. In a first example, the integrated circuit is operable in a first mode and in a second mode. In the first mode, the various parts are configured and interconnected in such a way that they operate together as a valley current mode regulator control circuit. In the second mode, the various parts are configured and interconnected in such a way that they operate together as a current-mode constant on-time mode regulator control circuit. In another example, a voltage regulator control integrated circuit has the same basic constituent parts and is operable in a first mode as a peak current mode regulator control circuit, or in a second mode as a constant off-time time mode regulator control circuit.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 5, 2021
    Assignee: Active-Semi, Inc.
    Inventor: Masashi Nogawa
  • Patent number: 11069624
    Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 20, 2021
    Assignee: Faraday Semi, Inc.
    Inventors: Martin Standing, Parviz Parto
  • Patent number: 11063516
    Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: July 13, 2021
    Assignee: Faraday Semi, Inc.
    Inventors: Seungbeom Kevin Kim, Jack Walter Cornish, III, Saurabh Anil Jayawant, Parviz Parto