Abstract: An automated system for identification of fabrication defects that lead to the failure of IC products. Design information of the product to be tested is analyzed to identify electrical node-to-node faults that can be caused by fabrication defects. The circuit is then analyzed to determine the electrical response to input patterns which result from the node-to-node faults. A matrix which relates failure responses to a multiplicity of input patterns as a function of process defects is constructed. This response matrix is used to identify the fabrication defect. In those cases in which the response matrix is degenerate, i.e. a set of output responses can arise from more than one fault, knowledge about the probability of occurrence of various defects is used to assign probabilities to the node-to-node faults which may generate the output response set. The system then takes knowledge of a specific IC test system and the response matrix to generate a set of test vectors to analyze a product.