Patents Assigned to Semiconductor Energy Laboratory Co., Ltd., Japanese corporation
  • Publication number: 20010048115
    Abstract: A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active layer of the p-channel type semiconductor device is added before forming the gate insulating film. Then, by applying thermal oxidation treatment to the active layer, the impurity element is subjected to redistribution, and the concentration of the impurity element in the principal surface of the active layer is minimized. The precise control of threshold voltage is enabled by the impurity element that is present in a trace quantity.
    Type: Application
    Filed: July 3, 2001
    Publication date: December 6, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japanese corporation
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Takeshi Fukunaga
  • Publication number: 20010045556
    Abstract: In a pixel structure of an active matrix liquid crystal display device, a common electrode branching out from a common line which is maintained at a specified voltage and a pixel electrode connected to a drain of a thin-film transistor arranged on a common plane are wound around each other in spiral form. Electric fields generally oriented parallel to a substrate are produced between the common electrode and pixel electrode arranged in each pixel on the substrate. These electric fields drive a liquid crystal material to provide a visual display. The pixel electrode is surrounded, or fenced off, by the common electrode in each pixel so that the former is kept unaffected from interference from a nearby gate line and/or source line.
    Type: Application
    Filed: July 27, 2001
    Publication date: November 29, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japanese corporation
    Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
  • Publication number: 20010041414
    Abstract: An active matrix circuit using top-gate type thin-film transistors is characterized in that an auxiliary capacitor is formed between a black matrix and an N-type or P-type active layer, and uses, as a dielectric, a silicon nitride layer used as a passivation film of an interlayer insulator. Also, an active matrix circuit using bottom-gate type thin-film transistors is characterized in that two auxiliary capacitors. One of the auxiliary capacitors is formed between a capacitor wiring line formed on a substrate and an N-type or P-type conductive region or a metal wiring line connected to the conductive region, and uses a gate insulating film as a dielectric. The other one of the auxiliary capacitors is formed between a black matrix and said N-type or P-type conductive region or said metal wiring line connected to the conductive region, and uses a silicon nitride layer used as a passivation film as a dielectric.
    Type: Application
    Filed: July 16, 2001
    Publication date: November 15, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd. Japanese Corporation
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Publication number: 20010038099
    Abstract: Two kinds of a thin film semiconductor unit are disposed over a substrate. A first thin film semiconductor unit includes a polycrystalline semiconductor thin film, and a second thin film semiconductor unit includes an amorphous semiconductor thin film.
    Type: Application
    Filed: March 19, 2001
    Publication date: November 8, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japanese corporation
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Takeshi Fukada
  • Publication number: 20010035919
    Abstract: A metal electrode also serving as a black matrix is so formed as to cover the periphery of an ITO pixel electrode. A region where the pixel electrode and the metal electrode coextend also serves as an auxiliary capacitor. Since the auxiliary capacitor can be formed by using a thin insulating film, it can have a large capacitance. By virtue of the structure in which the black matrix also serves as the auxiliary capacitor, it is not necessary to provide an electrode dedicated to the auxiliary capacitor, thereby preventing reduction in aperture ratio. Further, the black matrix can completely shield a source line and a gate line from light.
    Type: Application
    Filed: March 23, 2001
    Publication date: November 1, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd. Japanese corporation
    Inventor: Hongyong Zhang
  • Publication number: 20010029144
    Abstract: A process of a pixel electrode of a direct-sight type of reflection type liquid-crystal display device is simplified. A pixel electrode 120 of a reflection type liquid-crystal display device is formed of an aluminum film which is formed by sputtering. In forming the aluminum film, moisture is intentionally contained in atmosphere, and also a sample is heated. With this process, aluminum grains grow so that irregularities of &mgr;m order is formed on the surface of the aluminum film. The aluminum film thus formed allows the incident light to be irregularly reflected so that it is in a visually white muddy state. This is suitable to the pixel electrode for the reflection type liquid-crystal display device.
    Type: Application
    Filed: May 30, 2001
    Publication date: October 11, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japanese corporation
    Inventor: Hiroki Adachi
  • Publication number: 20010029098
    Abstract: A process for fabricating a semiconductor device having a multilayer wiring, comprising steps of: forming a first wiring or electrode on a substrate; forming an insulating film which covers the first wiring or electrode; forming a contact hole to the first wiring or electrode through the insulating film; forming a wiring for contacting the first wiring or electrode inside the contact hole; and removing the protruded portion of the contact wiring and flattening the insulating film at the same time in an electrolytic solution by means of chemical mechanical polishing using the contact wiring as the anode. Also claimed is an apparatus for polishing the surface of a semiconductor device during its fabricating the device, comprising: means for performing chemicomechanical polishing; and means for supplying electric current to the electrode of the semiconductor device.
    Type: Application
    Filed: May 24, 2001
    Publication date: October 11, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japanese corporation
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Publication number: 20010023105
    Abstract: Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel effect. The impurity regions 104 allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.
    Type: Application
    Filed: March 16, 2001
    Publication date: September 20, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., Japanese corporation
    Inventor: Shunpei Yamazaki
  • Publication number: 20010018239
    Abstract: In order to promote an effect of laser annealing in respect of a semiconductor film, moisture is intentionally included in an atmosphere in irradiating laser beam to the semiconductor film by which a temperature holding layer comprising water vapor is formed on the surface of the semiconductor film in irradiating the laser beam and the laser annealing operation can be performed effectively.
    Type: Application
    Filed: February 27, 2001
    Publication date: August 30, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japanese corporation
    Inventors: Naoto Kusumoto, Shunpei Yamazaki, Koichiro Tanaka
  • Publication number: 20010015714
    Abstract: A plurality of partial image display portions are provided. Each of the partial image display portions is formed by at least one signal line driver circuits and at least one of scanning line driver circuits. Each partial image display portion displays a part of one frame of image. The whole one frame of image is displayed by all of the partial image display portions.
    Type: Application
    Filed: April 12, 2001
    Publication date: August 23, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., Japanese corporation,
    Inventors: Shunpei Yamazaki, Jun Koyama, Hidehiko Chimura
  • Publication number: 20010013909
    Abstract: A structure is provided which avoids overlap of a pixel electrode and an intersecting portion of a gate line and a data line. For example, the pixel electrode is patterned such that its corner portion is intentionally cut out to avoid the intersecting portion. With this structure, the capacitance of a storage capacitor that is formed by an overlapping portion of the pixel electrode and a black matrix can be increased while short-circuiting in a third interlayer insulating film that is interposed between the pixel electrode and the black matrix is prevented.
    Type: Application
    Filed: April 23, 2001
    Publication date: August 16, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., Japanese corporation
    Inventors: Hongyong Zhang, Takeshi Fukunaga
  • Publication number: 20010007368
    Abstract: In a circuit configuration comprising an n-channel thin-film transistor and a p-channel thin-film transistor integrally produced on a single substrate, a lightly-doped drain (LDD) region is formed selectively in the n-channel thin-film transistor, and damages to semiconductor layers caused when implanting impurity ions are balanced between the n- and p-channel thin-film transistors. This configuration achieves a balance between the n- and p-channel thin-film transistors and thereby provides high characteristics CMOS circuit.
    Type: Application
    Filed: January 30, 2001
    Publication date: July 12, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd.,a Japanese corporation
    Inventors: Shunpei Yamazaki, Takeshi Fukunaga
  • Publication number: 20010000755
    Abstract: An interlayer insulating film (104) that is formed on a substrate(101) so as to cover TFTs(102, 103) is planarized by mechanical polishing that is typified by CMP. Pixel electrodes (106, 107) are formed on the interlayer insulating film(104) and an insulating layer(108) is formed so as to cover the pixel electrodes. The insulating layer(108) is planarized by second mechanical polishing so that the surfaces of the pixel electrodes become flush with those of resulting buried insulating layers(112, 113). Since the pixel electrode surfaces have no steps, such problems as alignment failures of a liquid crystal material and a contrast reduction due to diffused reflection of light can be prevented.
    Type: Application
    Filed: December 4, 2000
    Publication date: May 3, 2001
    Applicant: Semiconductor Energy Laboratory Co., Ltd., a Japanese Corporation
    Inventors: Yoshiharu Hirakata, Takeshi Fukada, Shunpei Yamazaki