Patents Assigned to Semiconductor Energy Laboratory
  • Publication number: 20240111385
    Abstract: A display device having a photosensing function is provided. A display device having a biometric authentication function typified by fingerprint authentication is provided. A display device having both a touch panel function and a biometric authentication function is provided. The display device includes a first substrate, a light guide plate, a first light-emitting element, a second light-emitting element, and a light-receiving element. The first substrate and the light guide plate are provided to face each other. The first light-emitting element and the light-receiving element are provided between the first substrate and the light guide plate. The first light-emitting element has a function of emitting first light through the light guide plate. The second light-emitting element has a function of emitting second light to a side surface of the light guide plate. The light-receiving element has a function of receiving the second light and converting the second light into an electric signal.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 4, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kubota, Ryo HATSUMI, Taisuke KAMADA
  • Publication number: 20240112629
    Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a display region, a first functional layer, and a second functional layer. The display region includes a pixel, and the pixel includes a display element and a pixel circuit. The first functional layer includes the pixel circuit, a scan line, and a first connection portion. The display element is electrically connected to the pixel circuit, and the pixel circuit is electrically connected to the scan line. The second functional layer includes a region overlapping with the first functional layer, the second functional layer includes a driver circuit and a wiring, and the driver circuit is provided so that the pixel circuit is positioned between the driver circuit and the display element. The wiring is electrically connected to the scan line at the first connection portion, and the wiring is electrically connected to the driver circuit.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei TOYOTAKA, Daiki NAKAMURA
  • Patent number: 11948515
    Abstract: A low-power display device is provided. The display device is provided with a plurality of display portions. A data driver circuit and an addition circuit are provided to have a region overlapping with the display portion. First analog data is output from the data driver circuit in the case where first digital data consisting of a first digital value is input to the data driver circuit, whereas second analog data is output from the data driver circuit in the case where second digital data consisting of a second digital value is input to the data driver circuit. The addition circuit generates analog data corresponding to digital data that has a high-order bit that is the first digital value and a low-order bit that is the second digital value, by adding the second analog data to the first analog data. An output terminal of the data driver circuit is directly connected to an input terminal of the addition circuit without through an amplifier circuit.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kiyotaka Kimura, Hidetomo Kobayashi, Kei Takahashi
  • Patent number: 11948626
    Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiya Saito, Yuto Yakubo, Tatsuya Onuki, Shuhei Nagatsuka
  • Patent number: 11947398
    Abstract: A sturdy electronic device is provided. A reliable electronic device is provided. A novel electronic device is provided. An electronic device includes a first board, a second board, a display portion having flexibility, and a power storage device having flexibility. The first board and the second board face each other. The display portion and the power storage device are provided between the first board and the second board. The display portion includes a first surface facing the power storage device. The first surface includes a first region not fixed to the power storage device. The first region overlaps with a display region of the display portion.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: April 2, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Masaaki Hiroki
  • Patent number: 11947228
    Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miyuki Hosoba, Junichiro Sakata, Hideaki Kuwabara
  • Patent number: 11950410
    Abstract: A semiconductor device with a large storage capacity per unit area can be provided. A memory cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor includes a stack including a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, a second insulator over the second conductor, and a third conductor over the second insulator; a first oxide arranged in a ring-like shape on a side surface of an opening portion of the second conductor; a fourth conductor arranged in a ring-like shape in contact with an inner wall of the first oxide; a cylindrical third insulator arranged to penetrate the stack, the first oxide, and the fourth conductor; and a second oxide arranged in contact with an inner wall of the third insulator.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 11950497
    Abstract: A light-emitting element with high emission efficiency and high reliability is provided. The light-emitting element includes a host material and a guest material in a light-emitting layer. The host material has a function of converting triplet excitation energy into light emission and the guest material emits fluorescence. The molecular structure of the guest material is a structure including a luminophore and protecting groups, and five or more protecting groups are included in one molecule of the guest material. The introduction of the protecting groups into the molecule inhibits energy transfer of triplet excitation energy by the Dexter mechanism from the host material to the guest material. As the protecting group, an alkyl group or a branched-chain alkyl group is used.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Nobuharu Ohsawa, Takuya Haruyama, Anna Tada
  • Patent number: 11948945
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes an oscillation circuit including a first coil, a second coil, a first capacitor, a second capacitor, a first transistor, and a second transistor and a frequency correction circuit including a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a switching circuit. The switching circuit has a function of controlling a conduction state or a non-conduction state of the third transistor and the fourth transistor. The frequency correction circuit is provided above the oscillation circuit and has a function of adjusting an oscillation frequency of the oscillation circuit. The first transistor and the second transistor each include a semiconductor layer containing silicon in a channel formation region. The third transistor and the fourth transistor each include a semiconductor layer containing an oxide semiconductor in a channel formation region.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuto Yakubo, Hitoshi Kunitake, Takayuki Ikeda
  • Patent number: 11950447
    Abstract: A novel light-emitting device with a microcavity structure which can improve the emission efficiency compared to the conventional one is provided. In a light-emitting device with a microcavity structure that emits light in a near-infrared range, reflectance of one or both of a first electrode (reflective electrode) and a second electrode (semi-transmissive and semi-reflective electrode) with respect to light in a near-infrared range (e.g., light with a wavelength of 850 nm) is higher than the reflectance thereof with respect to light in a visible light range (greater than or equal to 400 nm and less than 750 nm).
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeyoshi Watabe, Airi Ueda, Nobuharu Ohsawa, Satoshi Seo
  • Patent number: 11949061
    Abstract: A secondary battery, suitable for a portable information terminal or a wearable device is provided. An electronic device having a novel structure which can have various forms and a secondary battery that fits the forms of the electronic device are provided. In the secondary battery, sealing is performed using a film provided with depressions or projections that ease stress on the film due to application of external force. A pattern of depressions or projections is formed on the film by pressing, e.g., embossing.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minoru Takahashi, Ryota Tajima
  • Patent number: 11948959
    Abstract: An imaging device that generates, in a pixel, a potential higher than a potential to be supplied to the pixel is provided. The imaging device includes a pixel including a first circuit and a second circuit; the second circuit includes a photoelectric conversion device; the first circuit is electrically connected to the second circuit; the first circuit has a function of adding a first potential and a second potential to generate a third potential; and the second circuit has a function of generating data in the photoelectric conversion device to which the third potential is applied and has a function of outputting the data.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Naoto Kusumoto
  • Patent number: 11949021
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa
  • Patent number: 11950474
    Abstract: One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential can be supplied stably is provided. Further, a bendable display device to which a signal or a power supply potential can be supplied stably is provided. The display device includes, over a flexible substrate, a display portion, a plurality of connection terminals to which a signal from an outside can be input, and a plurality of wirings. One of the plurality of wirings electrically connects one of the plurality of connection terminals to the display portion. The one of the plurality of wirings includes a first portion including a plurality of separate lines and a second portion in which the plurality of lines converge.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
  • Publication number: 20240105855
    Abstract: A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Hitoshi KUNITAKE
  • Publication number: 20240107854
    Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Kensuke YOSHIZUMI
  • Patent number: 11942602
    Abstract: To provide a power storage device whose charge and discharge characteristics are unlikely to be degraded by heat treatment. To provide a power storage device that is highly safe against heat treatment. The power storage device includes a positive electrode, a negative electrode, a separator, an electrolytic solution, and an exterior body. The separator is located between the positive electrode and the negative electrode. The separator contains polyphenylene sulfide or solvent-spun regenerated cellulosic fiber. The electrolytic solution contains a solute and two or more kinds of solvents. The solute contains LiBETA. One of the solvents is propylene carbonate.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuhei Narita, Ryota Tajima, Teppei Oguni
  • Patent number: 11942483
    Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11942554
    Abstract: In a transistor that includes an oxide semiconductor, a change in electrical characteristics is suppressed and the reliability is improved. A semiconductor device that includes a transistor is provided. The transistor includes a first conductive film that functions as a first gate electrode, a first gate insulating film, a first oxide semiconductor film that includes a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film that function as a second gate electrode. The second oxide semiconductor film includes a region higher in carrier density than the first oxide semiconductor film. The second conductive film includes a region in contact with the first conductive film.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Yukinori Shima, Masataka Nakada, Masami Jintyou
  • Patent number: 11942132
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki