Patents Assigned to Semiconductor Energy Labortory Co., Ltd.
  • Patent number: 10672771
    Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Fumika Akasawa, Hiroki Inoue, Takashi Nakagawa, Yoshiyuki Kurokawa
  • Patent number: 10474186
    Abstract: A display device includes a display panel mounted on a curved surface, and driver circuits including circuit elements which are mounted on a plurality of plane surfaces provided on the back of the curved surface in a stepwise shape along the curved surface.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 12, 2019
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata
  • Patent number: 8431496
    Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 30, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventor: Satoshi Toriumi
  • Patent number: 8410486
    Abstract: A method for manufacturing a semiconductor device having favorable electric characteristics with high productivity is provided. A first microcrystalline semiconductor film is formed over an oxide insulating film under a first condition that mixed phase grains with high crystallinity are formed at a low particle density. After that, a second microcrystalline semiconductor film is stacked over the first microcrystalline semiconductor film under a second condition that a space between the mixed phase grains are filled by the crystal growth of the mixed phase grains of the first microcrystalline semiconductor film.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 2, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi
  • Patent number: 8405090
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 26, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 8395158
    Abstract: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor layer which is formed over the gate insulating film and is formed of a microcrystalline semiconductor, a second semiconductor layer which is formed over the first semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the second semiconductor layer are provided in the thin film transistor. A channel is formed in the first semiconductor layer when the thin film transistor is placed in an on state.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 8357551
    Abstract: A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takashi Hamada, Satoshi Seo
  • Patent number: 8059692
    Abstract: The present invention provides a laser oscillator using an electroluminescent material that can enhance directivity of emitted laser light and resistance to a physical impact. The laser oscillator has a first layer including a concave portion, a second layer formed over the first layer to cover the concave portion, and a light emitting element formed over the second layer to overlap the concave portion, wherein the second layer is planarized, an axis of laser light obtained from the light emitting element intersects with a planarized surface of the second layer, the first layer has a curved surface in the concave portion, and a refractive index of the first layer is lower than that of the second layer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: November 15, 2011
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Ryoji Nomura, Akihisa Shimomura
  • Patent number: 7732241
    Abstract: An object is to provide a microstructure in which shear stress of a structural layer is increased, a manufacturing method thereof, and a microelectromechanical system. A sacrificial layer is formed over a substrate. A metal film is formed over the sacrificial layer. The metal film is irradiated with a laser beam. Needle-like crystals of the metal film are reduced or eliminated. The metal film is etched and processed into a predetermined shape to form a metal layer. Then, the sacrificial layer is removed. Accordingly, a microelectromechanical system which is excellent in reliability and in which a resistance property to breakage of a movable portion of the microstructure is improved can be provided.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi, Kojiro Shiraishi
  • Patent number: 7733441
    Abstract: It is an object of the present invention to provide a lighting system having favorable luminance uniformity in a light-emitting region when the lighting system has large area. According to one feature of the invention, a lighting system comprises a first electrode, a second electrode, a layer containing a light-emitting substance formed between the first electrode and the second electrode, an insulating layer which is formed over a substrate in a grid form and contains a fluorescence substance, and a wiring formed over the insulating layer. The insulating layer and the wiring are covered with the first electrode so that the first electrode and the wiring are in contact with each other.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Satoshi Seo, Yasuyuki Arai
  • Publication number: 20090140231
    Abstract: It is an object of the present invention to provide a technique in which a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield. A memory device according to the present invention has a first conductive layer including a plurality of insulators, an organic compound layer over the first conductive layer including the insulators, and a second conductive layer over the organic compound layer.
    Type: Application
    Filed: April 25, 2006
    Publication date: June 4, 2009
    Applicant: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Mikio Yukawa, Nobuharu Ohsawa, Yoshinobu Asami, Ikuko Kawamata, Shunpei Yamazaki
  • Patent number: 7060511
    Abstract: The present invention provides a method for estimating resistance value of an LDD region that works in an actual FET and forming an optimum LDD region. Therefore, the present invention provides an FET in which OFF (leakage) current is reduced and has superior switching characteristics. An equivalent circuit is assumed so as to estimate an external resistance value. The equivalent circuit is a circuit in which an external resistor is serially-connected to the drain side of a conventional FET. And the threshold voltage and the external drain voltage—drain current characteristics of the FET having an LDD structure are measured, and the result is applied to the equivalent circuit. Regarding an external drain voltage when drain current is saturated as an external saturation drain voltage, a saturation drain voltage in an imaginary FET taking off the external resistor from the estimating FET is obtained from the threshold voltage.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: June 13, 2006
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventor: Tatsuya Honda
  • Patent number: 5972437
    Abstract: To promote the characteristic of an interface between a gate insulating film and a semiconductor and control the threshold voltage, in forming the insulating film, a surface on which the insulating film is to be formed is previously exposed to activated oxygen and thereafter, the insulating film is formed on the surface, or in steps of manufacturing a thin film transistor, the insulating film is formed with monosilane, dinitrogen monoxide and oxygen as raw materials.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: October 26, 1999
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Tatsuya Ohori, Michiko Takei, Hongyong Zhang, Hiroshi Kuroki