Abstract: A reactor for processing a semiconductor substrate includes a reactor housing which defines a processing chamber, and at least one gas injecting assembly. The processing chamber is adapted to support a semiconductor substrate therein. The gas injection assembly injects at least one gas into the processing chamber and onto the substrate and is adapted to ionize the gas injection into the processing chamber to increase the reactivity of the gas with the substrate to thereby enhance the processing of the semiconductor substrate. In preferred form, the gas is ionized into a gas plasma. For example, the gas injection assembly may include a gas plasma generator which ionizes the gas with an electromagnetic field. Preferably, the gas plasma generator ionizes the gas exteriorly of the processing chamber to isolate the substrate from the plasma generator.

Abstract: Apparatus for rapidly and precisely removing and replacing surface mount devices without disturbance to nearby devices on a printed circuitboard, the invention utilizes a multiple nozzle arrangement wherein nozzles arranged for reciprocating motion one each along each edge of a surface mount device direct low velocity hot gas against bond joint locations along the respective edges of the surface mount device, thereby to melt the bonding agent mounting the device to the circuitboard. The multiple nozzle arrangement of the present system thus allows removal and/or replacement of devices of widely varying dimensions without the need for changes in nozzle size such as is inherent in prior art hot gas rework stations.

Abstract: A step-and-repeat exposure system incorporates a method for achieving die-by-die alignment at high speed in order to increase the throughput of the system. In order to align circuit patterns which are to be exposed onto a semiconductor wafer in an overlapping fashion, the wafer is initially moved to a target position in order to view an alignment target previously formed on the wafer, and is subsequently moved to an exposure position. The movement to the exposure position is controlled as a function of the calculated position of the alignment target. The method involves initiating the video scan to view the alignment target prior to the stage coming to a complete rest at the target position. The characteristics of the stage motion are determined and the acquisition of the video data is initiated as soon as the oscillation of the stage has subsided by an acceptable amount. By initiating the video scan at an early point, a significant decrease in the alignment time at each die site is achieved.

Abstract: In this laser pattern generator, plural laser beams are arranged in a closely spaced, noninterfering array. The beams are concurrently deflected across a region of the target surface by an acousto-optic deflector driven by a swept frequency drive signal. The target is moved perpendicular to the direction of deflection to reposition it for exposure during the next stroke of the beams. The extent of target offset in the direction of deflection is measured and used to control initiation of modulation during each deflection stroke, so that each portion of the generated pattern begins from a uniform reference line on the target. Pattern data is supplied to the beam modulators in accordance with data clock pulses the repetition rate of which is established by the rate of change of frequency of the deflector drive signal.

Abstract: In this step and repeat wafer direct exposure system, the initial reticle contains an alignment target which is repetitively exposed onto the semiconductor wafer at each circuit image location. Each subsequently used reticle contains a complementary shaped alignment pattern. At each array location, a low intensity light source is used for through-the-camera-lens alignment. Viewing optics and a video camera are used simultaneously to view the virtual image of the alignment target situated on the wafer and the corresponding alignment pattern situated on the reticle. While viewing, the stage is moved to achieve perfect alignment, after which the circuit pattern is exposed from the reticle onto the wafer. The wafer then is stepped and the process repeated at other array positions.The apparatus includes an air gauge system for automatically locating the wafer center and aligning the wafer below the exposure camera.

Abstract: This automatic wafer alignment technique may be used in a step-and-repeat photomicrolithographic exposure system accurately to prealign a wafer before exposure to the B-level and subsequent reticles, and automatically to align the wafer at each die site prior to exposure. A search technique optimizes location of the global targets used for wafer prealignment. The search begins at the most likely target position and proceeds through a search area established by the maximum expected rough prealignment error. A wafer alignment target configuration consisting of a cross with one elongated arm and a short crossbar is used to optimize target verification. To locate targets a video image is digitized and the average intensity at each video scan line and column is obtained and stored. This data is used to determine the presence in the video image of feature edges. A table of all such edges is established. These listed edges are correlated to determine all pairs of edges that may represent potential targets.

Abstract: A mask illumination system for use in the production of semiconductor devices includes an optical assembly having an internal focal plane corresponding to the mask. A reticle edge masking assembly (REMA) is located at the internal focal plane and serves to define a pattern of light which is projected onto the mask. The provision of the reticle edge masking assembly in a focal plane separate from the mask plane serves to reduce blurriness caused by near field diffraction, as well as facilitating the use of more complex REMA assemblies.

Abstract: A masking apparatus for use in the production of semiconductor devices. In order to achieve alignment beween successive masking operations, alignment targets are formed on a semiconductor wafer adjacent circuit patterns which are exposed onto the wafer. The alignment targets are viewed during subsequent masking steps in order to align the previously exposed circuit patterns with a new pattern contained on a reticle. In many masking steps, the alignment target is covered with one or more highly reflective films, which decreases the ability to view the alignment target. A phase contrast microscope is utilized to enable the embedded alignment targets to be viewed despite the existence of the overlying reflective films. The micrscope incorporates an illumination subsystem containing an annular diaphragm and an observation subsystem containing a phase plate.