Patents Assigned to Semiconductor Insights, Inc.
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Patent number: 8701058Abstract: The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.Type: GrantFiled: June 17, 2010Date of Patent: April 15, 2014Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Edward Keyes
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Patent number: 8606041Abstract: A schematic diagram detailing a circuit that was reverse engineered from a plurality of images taken of the circuit is provided. The schematic diagram includes at least one circuit element that was represented as an object in at least one of the plurality of images, such that signal continuity information was determined through local tracing of connectivity between a first image and a second image of the plurality of images. A method of tracing the connectivity within the plurality of images to produce the schematic diagram is also disclosed.Type: GrantFiled: February 11, 2008Date of Patent: December 10, 2013Assignee: Semiconductor Insights, Inc.Inventors: Edward Keyes, Vyacheslav L. Zavadsky
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Publication number: 20130118896Abstract: There is provided a method, system and computer program product to delayer a layer of a sample, the layer comprising one or more materials, in an ion beam mill by adjusting one or more operating parameters of the ion beam mill and selectively removing each of the one or more materials at their respective predetermined rates. There is also provided a method and system for obtaining rate of removal of a material from a sample in an ion beam mill.Type: ApplicationFiled: November 9, 2012Publication date: May 16, 2013Applicant: SEMICONDUCTOR INSIGHTS INC.Inventor: Semiconductor Insights Inc.
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Patent number: 8347262Abstract: A method, computer-readable medium and system are described for deriving a schematic diagram representative of an integrated circuit (1C) comprising a plurality of circuit elements. In general, the method, computer-readable medium and system are configured to receive as input a working schematic diagram identifying at least some of the circuit elements, and at least one existing schematic diagram from one or more libraries thereof. Based on this input, at least a portion of the working schematic diagram that matches at least a portion of the at least one existing schematic diagram is identified and replaced, thereby forming a revised schematic diagram.Type: GrantFiled: April 18, 2008Date of Patent: January 1, 2013Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav Zavadsky, Edward Keyes, Shane Edmonds, Alexei Novikov
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Patent number: 8219940Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.Type: GrantFiled: July 6, 2005Date of Patent: July 10, 2012Assignee: Semiconductor Insights Inc.Inventors: Mohammed Ouali, Jason Abt, Edward Keyes, Vyacheslav Zavadsky
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Publication number: 20120117085Abstract: A method of normalizing a bibliographic field of a structured field relational database is disclosed. The method comprises weighting potential candidate records according to the value in the corresponding field in the records, together with other related fields in the candidate record and other related records in the database. Each of the candidate records is successively evaluated and compared against an acceptable threshold. If the weight exceeds the threshold, the candidate record is returned from the query. Otherwise, a new entry in the database is created. Optionally, before creating such a new entry, the highest weighted candidate record may be compared against a minimally acceptable threshold and if the weight exceeds such lower threshold, the candidate is returned from the query.Type: ApplicationFiled: January 13, 2012Publication date: May 10, 2012Applicant: SEMICONDUCTOR INSIGHTS INC.Inventor: Jason M. White
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Publication number: 20120117086Abstract: A method of normalizing a bibliographic field of a structured field relational database is disclosed. The method comprises weighting potential candidate records according to the value in the corresponding field in the records, together with other related fields in the candidate record and other related records in the database. Each of the candidate records is successively evaluated and compared against an acceptable threshold. If the weight exceeds the threshold, the candidate record is returned from the query. Otherwise, a new entry in the database is created. Optionally, before creating such a new entry, the highest weighted candidate record may be compared against a minimally acceptable threshold and if the weight exceeds such lower threshold, the candidate is returned from the query.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: SEMICONDUCTOR INSIGHTS INC.Inventor: Jason M. White
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Patent number: 8122053Abstract: A method of normalizing a bibliographic field of a structured field relational database is disclosed. The method includes weighting potential candidate records according to the value in the corresponding field in the records, together with other related fields in the candidate record and other related records in the database. Each of the candidate records is successively evaluated and compared against an acceptable threshold. If the weight exceeds the threshold, the candidate record is returned from the query. Otherwise, a new entry in the database is created. Optionally, before creating such a new entry, the highest weighted candidate record may be compared against a minimally acceptable threshold and if the weight exceeds such a lower threshold, the candidate is returned from the query.Type: GrantFiled: January 7, 2008Date of Patent: February 21, 2012Assignee: Semiconductor Insights, Inc.Inventor: Jason M. White
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Patent number: 8051395Abstract: The present invention seeks to provide a simple, but novel regime, for re-labelling swappable pins that permits swappability information to be maintained without significantly increasing computational complexity and is conducive to inexact pattern matching for the purposes of developing more complex logical processing blocks from elementary components in design analysis. The method comprises a recursive application of a simple labelling procedure. This method is repeated recursively until all gate instances in the circuit fragment have been assigned a swappability number.Type: GrantFiled: May 16, 2008Date of Patent: November 1, 2011Assignee: Semiconductor Insights Inc.Inventors: Sergei Sourjko, Vyacheslav Zavadsky
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Patent number: 7899640Abstract: There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.Type: GrantFiled: July 31, 2008Date of Patent: March 1, 2011Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Mykola Sherstyuk
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Patent number: 7886258Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.Type: GrantFiled: June 15, 2010Date of Patent: February 8, 2011Assignee: Semiconductor Insights, Inc.Inventors: Mohammed Ouali, Jason Abt, Edward Keyes, Vyacheslav Zavadsky
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Patent number: 7873203Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: GrantFiled: August 29, 2008Date of Patent: January 18, 2011Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20100257501Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.Type: ApplicationFiled: June 15, 2010Publication date: October 7, 2010Applicant: Semiconductor Insights Inc.Inventors: Mohammed OUALI, Jason Abt, Edward Keyes, Vyacheslav Zavadsky
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Patent number: 7765517Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.Type: GrantFiled: October 24, 2007Date of Patent: July 27, 2010Assignee: Semiconductor Insights Inc.Inventors: Mohammed Ouali, Jason Abt, Edward Keyes, Vyacheslav Zavadsky
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Patent number: 7751643Abstract: The present invention provides a method and apparatus for reducing uneven brightness in an image from a particle based image system. This uneven brightness is most often seen as regions of shadow, but may also be seen as regions of over brightness. In cases where the uneven brightness is in the form of shadowing, the method corrects for the shadowy regions by first identifying the area of shadow, obtaining brightness information from a region near the shadow, where the brightness is optimal, applying statistical methods to determine the measured brightness as a regression function of the optimal brightness, and number and proximity of shadowy objects, then correcting the shadow area brightness by calculating the inverse of the function of the shadow brightness. With this method, the brightness within the shadowy or over brightness regions are corrected to appear at a substantially similar level of brightness as the region of optimal brightness in the image.Type: GrantFiled: August 12, 2004Date of Patent: July 6, 2010Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Jason Abt
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Patent number: 7693348Abstract: A method of registering and vertically aligning multiply-layered images into a mosaic is described. The method comprises performing an iterative process of vertical alignment of layers into a mosaic using a series of defined alignment correspondence pairs and global registration of images in a layer using a series of defined registration correspondence points and then redefining the identified alignment correspondence pairs and/or registration correspondence points until a satisfactory result is obtained. Optionally, an initial global registration of each layer could be performed initially before commencing the alignment process. The quality of the result could be determined using a least squares error minimization or other technique.Type: GrantFiled: August 10, 2005Date of Patent: April 6, 2010Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav Zavadsky, Jason Abt, Mark Braverman, Edward Keyes, Vladimir Martincevic
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Patent number: 7643665Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: GrantFiled: August 31, 2004Date of Patent: January 5, 2010Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20090228518Abstract: A method and system for organizing and managing claim elements and reference objects is disclosed. The method and system establish database links between claim elements and reference objects based on associations identified between them. These database links are then stored in the database for future reference. The links are also used to derive additional associations between other claim elements and reference objects. The method and the system also enable the displaying of claim elements and reference objects to users in a way that illustrates the associations between the claim elements and reference objects. Associations may be defined based on similarities or dissimilarities between claim elements and reference objects, and amongst claim elements and reference objects, respectively.Type: ApplicationFiled: August 30, 2007Publication date: September 10, 2009Applicant: Semiconductor Insights, Inc.Inventors: Linda Wallace, Vyacheslav Zavadsky, Edward Keyes, Jason White
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Patent number: 7580557Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.Type: GrantFiled: August 29, 2008Date of Patent: August 25, 2009Assignee: Semiconductor Insights Inc.Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
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Publication number: 20090119623Abstract: The present invention seeks to provide a simple, but novel regime, for re-labelling swappable pins that permits swappability information to be maintained without significantly increasing computational complexity and is conducive to inexact pattern matching for the purposes of developing more complex logical processing blocks from elementary components in design analysis. The method comprises a recursive application of a simple labelling procedure. This method is repeated recursively until all gate instances in the circuit fragment have been assigned a swappability number.Type: ApplicationFiled: May 16, 2008Publication date: May 7, 2009Applicant: SEMICONDUCTOR INSIGHTS INC.Inventors: Sergei Sourjko, Vyacheslav Zavadsky