Abstract: A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.