Abstract: A method for forming a semiconductor integrated circuit device, e.g., MOS, CMOS. The method includes providing a semiconductor substrate, e.g., silicon substrate, silicon on insulator. The method includes forming a dielectric layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the semiconductor substrate. The method also includes forming a gate layer (e.g., polysilicon) overlying the dielectric layer. The method patterns the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. In a specific embodiment, sidewall spacers are formed using portions of the dielectric layer. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer.

Abstract: Techniques for an integrated circuit device are provided. The integrated circuit device includes a substrate, an active circuit area, and a dielectric layer. A seal ring surrounds the active circuit area. At least one corner area of the integrated circuit includes a plurality of corner band stacks. Each of the plurality of corner band stacks is oriented at about a predetermined angle and extends from a first sawing trace to a second sawing trace. In a specific embodiment, if a structural fault in the at least one corner area occurs, the structural fault is predisposed to extend at about the predetermined angle.

Abstract: A partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material (e.g., silicon/germanium, silicon carbide) in an etched source region and an etched drain region. Preferably, the etched source region and the etched drain region are coupled to the gate structure.

Abstract: Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide.