Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, which include a first region having a first transistor and a second region having a second transistor, the first transistor having a working current smaller than the second transistor. The semiconductor device further includes a first gate electrode on the first region of the base substrate, a second gate electrode on the second region of the base substrate and having an undercut structure, a first source/drain doped region in the base substrate on both sides of the first gate electrode, and a second source/drain doped region in the base substrate on both sides of the second gate electrode.

Abstract: A method for fabricating a semiconductor device includes providing a to-be-etched layer, including alternately arranged first regions and second regions along a first direction; forming a first mask layer on the to-be-etched layer; and forming a top mask layer on the first region and extending to the second region along the first direction. The projection pattern of the top mask layer divides the first mask layer formed on the first region into portions arranged in a second direction that is perpendicular to the first direction. The method further includes removing a portion of the first mask layer formed on the first region on both sides of the top mask layer to form a first trench. The first mask layer on the first region under the top mask layer forms a separation mask layer which divides the first trench into portions arranged in the second direction.

Abstract: One form of a method for manufacturing a semiconductor structure includes: providing a base, where the base includes a substrate and a plurality of discrete fins located on the substrate, a device region and an isolation region that are adjacent to each other, a metal gate structure formed on the substrate, where the metal gate structure spans the fins and covers parts of the tops and parts of side walls of the fins, an interlayer dielectric layer that is formed on the substrate exposed by the metal gate structure, where the interlayer dielectric layer covers a side wall of the metal gate structure; performing dry etching, where the metal gate structure in the isolation region and the fins located below the metal gate structure are sequentially etched to form an isolation trench surrounded by the interlayer dielectric layer and the remaining base; and forming an isolation structure in the isolation trench to simplify process steps of forming an isolation structure.

Abstract: A semiconductor structure and a forming method thereof are provided.

Abstract: A flash memory device includes a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, a gap structure between the gate structures, and a second isolation region filling an upper portion of the gap structure and leaving a first air gap in a lower portion of the gap structure.

Abstract: Semiconductor structure and method for forming semiconductor structure are provided. A substrate is provided, including a first dielectric layer, a first conductive layer and a second conductive layer. A first stop layer is formed on a top surface of the first conductive layer and a top surface of the second conductive layer, and a second stop layer is formed on a surface of the first dielectric layer. A second dielectric layer is formed on a surface of the first stop layer and a surface of the second stop layer. A first opening and a second opening are formed in the second dielectric layer by etching a portion of the second dielectric layer until the surface of the first stop layer is exposed. The first opening exposes the first stop layer on the first conductive layer, and the second opening exposes the first stop layer on the second conductive layer.

Abstract: Semiconductor device and fabrication method are provided. A plurality of first-type fin groups and second-type fins, each between the first-type fin groups, are formed on a substrate. A first-type fin group includes first-type fins. The first-type fins and the second-type fins are arranged in a direction perpendicular to an extending direction of the first-type fins and the second-type fins. The second-type fins are removed to form first trenches between corresponding first-type fin groups. A protective layer is formed on sidewalls of the first trenches after removing the second-type fins. The protective layer covers sidewalls of the first-type fins that are perpendicular to a width direction of the first-type fins. Second trenches are formed in the substrate under the first trenches by etching the substrate at bottoms of the first trenches using the protective layer as an etch mask.

Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a substrate with a first doped region and a second doped region; forming discrete first isolation structures in the second doped region; forming a third doped region in the second doped region between adjacent first isolation structures and under the first isolation structures; forming a gate structure; forming a source region in the first doped region; and forming a drain region in the second doped region. The first doped region includes first doping ions and the second doped region includes second doping ions with a conductivity type opposite to a conductivity type of the first doping ions. The third doped region includes third doping ions with a conductivity type opposite to the conductivity type of the second doping ions. A portion of the first isolation structure is located between the gate structure and the drain region.

Abstract: Embodiments of the present disclosure provide a detection method and apparatus, an electronic device, and a storage medium. In one form, the detection method includes: providing a layout graphic and a scan graphic; superimposing and comparing the layout graphic and the scan graphic, and extracting a sample non-overlapping pattern; encoding the sample non-overlapping pattern, to form sample coded data; using the sample coded data as input data of machine learning, to obtain a detection model library; and detecting a defect point of a to-be-detected device by using the detection model library. The present disclosure can improve the accuracy of defect point analysis, thereby accelerating the development of technology and improving the production efficiency.

Abstract: A semiconductor structure and a method for forming the same are provided. One form of a forming method includes: providing a base, the base including a device region and a dummy device region, the base including an isolation layer, gate structures located on the isolation layer, a first mask layer located on the gate structures, a source-drain plug located between the gate structures and on the isolation layer, and a second mask layer located on the source-drain plug. In implementations of the present disclosure, the first mask layer and the second mask layer on the dummy device region are separately removed. Correspondingly, the first opening and the second opening respectively expose the gate structures and the source-drain plug in the dummy device region. The gate structures exposed by the first opening and the source-drain plug exposed by the second opening are removed in the same step.

Abstract: Semiconductor structures and fabrication methods are provided. The method includes providing a to-be-etched layer having first regions, second regions and third regions; forming a first core layer on a first region; forming a first sidewall spacer on sidewalls of the first core layer; forming a sacrificial layer covering a portion of the first sidewall spacer on the to-be-etched layer, having a plurality of initial first openings and with a portion of the initial first opening exposing a portion of the first sidewall spacer on the second region; removing the portion of the first sidewall spacer exposed by the portion of the initial first opening to form a first opening; forming a second sidewall spacer in the first opening; and forming second openings in the sacrificial layer. The second openings expose one of or both a portion of the first sidewall spacer and a portion of the second sidewall spacer.

Abstract: Semiconductor device and method of forming a semiconductor device are provided. A substrate is provided, and first gate structures and source/drain doped layers are formed on the substrate. A dielectric layer is formed on the substrate, covering the first gate structures and source/drain doped layers. A first groove is formed in the dielectric layer exposing the source/drain doped layer. The first groove includes a first-groove bottom part and a first-groove top part. The first-groove top part is larger than the first-groove bottom part, and a sidewall of the first-groove top part is recessed more into the dielectric layer with respect to a sidewall of the first-groove bottom part. A first conductive structure is formed in the first-groove bottom part, and an insulating layer is formed in the first-groove top part. A second conductive structure, connected to the first gate structure, is formed in the dielectric layer.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, which includes a first region, a second region, and a third region. The semiconductor structure also includes a first fin, a second fin, and a third fin formed on the first, second, and third regions, respectively. Moreover, the semiconductor structure includes an isolation layer formed on the substrate, and a portion of sidewall surface of each of the first, second, and third fins. In addition, the semiconductor structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer formed on the first, second, and third fins, respectively. Two sides of the third epitaxial layer are in contact with the first epitaxial layer and the second epitaxial layer, respectively. Further, the semiconductor structure includes a conductive structure formed on the first, second, and third epitaxial layers.

Abstract: A method for forming a semiconductor device includes forming a gate structure on a substrate, and a doped source/drain region on each side of the gate structure; forming a first interlayer dielectric layer, the top surface of the first interlayer dielectric layer leveled with the top surface of the gate structure; forming a contact hole in the first interlayer dielectric layer on each side of the gate structure; forming a cobalt layer in the contact hole, the top surface of the cobalt layer lower than the top surface of the first interlayer dielectric layer; forming a protective layer to cover the cobalt layer, the top layer of the protective layer lower than the top surface of the first interlayer dielectric layer; and forming a second interlayer dielectric layer, the top surface of the second interlayer dielectric layer leveled with the top surface of the first interlayer dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having an opening and forming a first gate layer in the opening. The first gate layer closes a top of the opening and includes a void. The method also includes forming a second gate layer on the first gate layer. An atomic radius of a material of the second gate layer is smaller than gaps among the atoms of the material of the first gate layer. Further, the method includes performing a thermal annealing process to cause atoms of the material of the second layer to pass through the first gate layer to fill the void.

Abstract: Semiconductor structure and method of forming a semiconductor structure are provided. A substrate is provided, including a first region and a second region that are adjacent to each other and arranged in a first direction. Fins are disposed on a surface of the substrate at the first region, and first openings are located between adjacent fins. The fins include fins to-be-removed. A first dielectric layer is formed on sidewalls of the fins. The first dielectric layer fills the first openings. A first groove is formed in the substrate at the second region by etching the substrate at the second region using the first dielectric layer as a mask. After forming the first groove, a second groove is formed in the substrate at the first region by removing the fins to-be-removed and a portion of the substrate located at bottoms of the fins to-be-removed.

Abstract: A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Abstract: Fabrication method and semiconductor device are provided. The method includes: providing a base substrate including a first region and a second region adjacent to the first region, with first fins disposed on the base substrate in the first region and on the base substrate in the second region, and initial openings disposed between adjacent first fins; forming sidewall spacers on sidewalls of the first fins to form openings from the initial openings; and forming the second fins in the openings of the second region.

Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a substrate, and the substrate includes isolation structures; forming a first gate structure on the substrate; forming a first opening and a second opening at two sides of the first gate structure respectively, where the first opening is disposed between the first gate structure and the isolation structures, and at least a portion of sidewalls of the first opening exposes sidewalls of the isolation structure; performing a surface treatment on surface of inner walls of the first opening; and forming epitaxial layers in the first opening and in the second opening respectively, after the surface treatment.