Patents Assigned to SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING)
  • Patent number: 9111973
    Abstract: An elastic retention wheel and a wafer adapter containing this wheel are disclosed. The elastic retention wheel comprises: a rim; a retention main body positioned within the rim; and a plurality of spokes. Each spoke is positioned in a space between the rim and the retention main body. One end of each spoke is coupled to the retention main body, and the other end is coupled to the rim. A sliding rail can be provided on an inner side of the rim, and the spoke's other end can slide with the sliding rail. When the elastic retention wheel is stressed by a non-uniform or excessive external force, these spokes provide enhanced support from the rim's inner side, or at least partially disperse the non-uniform external force applied to the elastic retention wheel. Thereby, the elastic retention wheel is largely kept from over-deformation or cracking.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: August 18, 2015
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING)
    Inventor: Yujie Zhao
  • Patent number: 9087845
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube portion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 21, 2015
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING)
    Inventors: Xinpeng Wang, Haiyang Zhang
  • Publication number: 20130248946
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)
    Inventor: Mieno FUMITAKE
  • Publication number: 20130168741
    Abstract: The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening.
    Type: Application
    Filed: September 25, 2012
    Publication date: July 4, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (Beijing), Semiconductor Manufacturing International Corporation (Shanghai)
    Inventors: Semiconductor Manufacturing International (Shanghai), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (Beijing)
  • Publication number: 20130168861
    Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects.
    Type: Application
    Filed: October 30, 2012
    Publication date: July 4, 2013
    Applicants: Semiconductor Manufacturing International Corporation (Beijing), Semiconductor Manufacturing International Corporation (Shanghai)
    Inventors: Semiconductor Manufacturing International Corporation (Shanghai), Semiconductor Manufacturing International Corporation (Beijing)
  • Patent number: 8466065
    Abstract: This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 18, 2013
    Assignee: Semiconductor Manufacturing International Corporation (Beijing)
    Inventor: Wanchun Ren
  • Publication number: 20130119496
    Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.
    Type: Application
    Filed: October 17, 2012
    Publication date: May 16, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)
    Inventors: SEMICONDUCTOR MANUFACTURING INTERNA, SEMICONDUCTOR MANUFACTURING INTERNA