Abstract: A semiconductor structure and a forming method of a semiconductor structure are provided.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. One form of a forming method includes: providing a base; forming a plurality of discrete mandrel layers on the base, where an extending direction of the mandrel layers is a first direction, and a direction perpendicular to the first direction is a second direction; forming a plurality of spacer layers covering side walls of the mandrel layers; forming a pattern transfer layer on the base, where the pattern transfer layer covers side walls of the spacer layers; forming a first trench in the pattern transfer layer between adjacent spacer layers in the second direction; removing a mandrel layer to form a second trench after the first trench is formed; and etching the base along the first trench and the second trench to form a target pattern by using the pattern transfer layer and the spacer layer as a mask. In the present disclosure, the accuracy of the pattern transfer is improved.

Abstract: An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided.

Abstract: A method for forming a semiconductor device includes providing a substrate, forming an oxide layer over the substrate, forming a plurality of first gate oxide layers by etching the oxide layer, forming a second gate oxide layer between adjacent first gate oxide layers, forming a silicon layer over the plurality of first gate oxide layers and the second gate oxide layer, and etching the plurality of first gate oxide layers, the silicon layer, and the second gate oxide layer to expose the substrate, thereby forming a plurality of gate structures. The first gate oxide layer of the plurality of first gate oxide layers has sloped sidewalls. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer. Each gate structure includes an etched first oxide layer, a portion of the second gate oxide layer, and a portion of the silicon layer.

Abstract: A method for fabricating a semiconductor structure includes forming fin structures on a base substrate; and forming dummy gate structures and first initial isolation structures. Along the extension direction of the dummy gate structures, both sides of each first initial isolation structure are in contact with a dummy gate structure. The method includes forming a first dielectric layer on the base substrate, the top and sidewall surfaces of the fin structures, and the sidewall surfaces of the dummy gate structures and the first initial isolation structure; removing the dummy gate structures to form dummy gate openings; and removing a portion of each first initial isolation structure along the width direction of the fin structures to form a first isolation structure. Along the width direction of the fin structures, the first isolation structure has a top dimension smaller than a bottom dimension. The method further includes forming gate structures.

Abstract: A semiconductor structure and a forming method thereof are provided, and the forming method includes: providing a base; forming, on the base, a plurality of conductive function layers extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer located on the base between the conductive function layers, and a blocking structure located in the conductive function layer, the blocking structure segmenting the conductive function layers located on two sides of the blocking structure in the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive function layers, and the blocking structure; etching the top dielectric layer located above a junction of the blocking structure and the conductive function layer and a part of the blocking structure located at a side wall of the conductive function layer, to form a via running through the top dielectric layer and exposing a part of a top and a part of a side wall of the conductive fu

Abstract: The present disclosure provides an LDMOS device and a manufacturing method thereof.

Abstract: A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a base substrate, forming a plurality of discrete core layers on the base substrate, forming an isolation layer on a top surface of a core layer, forming a sacrificial layer on the base substrate and exposing a top surface of the isolation layer, removing the isolation layer after forming the sacrificial layer, removing the sacrificial layer after removing the isolation layer, forming a mask layer on a sidewall surface of the core layer after removing the sacrificial layer, and removing the core layer after forming the mask layer.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a to-be-etched layer including a first region; forming a first pattern material layer on the to-be-etched layer; forming a sacrificial layer on the first pattern material layer; forming a first opening in the sacrificial layer over the first region, where the first opening exposes a first portion of the first pattern material layer; forming a first doped region in the first pattern material layer using the sacrificial layer as a mask; forming a second opening in the sacrificial layer over the first region, where the second opening exposes a second portion of the first pattern material layer; and forming a second doped region in the first pattern material layer using the sacrificial layer as a mask, where the second doped region is connected with the first doped region.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of semiconductor fin structures formed on the semiconductor substrate; a plurality of gate structures, each formed on a semiconductor fin structure; a source electrode and a drain electrode formed on two opposite sides of each gate structure, wherein, at least a portion of the source electrode and at least a portion of the drain electrode are formed in the semiconductor fin structure; a covering layer formed on the semiconductor fin structures and also on two side surfaces of each gate structure; and an interlayer dielectric layer formed on the covering layer, wherein the interlayer dielectric layer covers each source electrode and each drain electrode, a trench is formed in the interlayer dielectric layer to expose a portion of each semiconductor fin structure, and a gate structure is formed in each trench.

Abstract: A semiconductor device and its fabrication method are provided. The method includes forming a core layer on a first region of a base substrate layer; forming sidewall spacer layers on sidewalls of two sides of the core layer along a first direction; forming a filling layer on a second region between adjacent sidewall spacer layers which are arranged along the first direction; forming a first dividing trench in the filling layer on the second region to divide the filling layer along a second direction, where sidewalls of the first dividing trench, arranged along the first direction, expose corresponding sidewall spacer layers; forming a second dividing trench in the core layer to divide the core layer along the second direction; forming a second dividing layer in the second dividing trench when forming a first dividing layer in the first dividing trench; and removing the filling layer and the core layer.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a layer to-be-etched including first regions and second regions. A second region includes a second trench region. The method also includes forming a first mask layer over the first and second regions, and forming first trenches discretely in the first mask layer in the first regions. Moreover, the method includes forming a divided doped layer, and implanting dopant ions into the first mask layer disposed outside the second trench region. In addition, the method includes forming a mask sidewall spacer on a sidewall of a first trench after forming the divided doped layer and implanting the dopant ions into the first mask layer disposed outside the second trench region. Further, the method includes forming a second trench in the first mask layer in the second region.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a bit line, a first word line, a source line, and a memory cell. The memory cell includes a first switch transistor and a magnetic tunnel junction. A first side of the magnetic tunnel junction is connected to a first terminal of the first switch transistor. The bit line is connected to a second terminal of the first switch transistor. The source line is connected to a second side of the magnetic tunnel junction. The first word line is connected to a third terminal of the first switch transistor.

Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a substrate and a fin protruding from the substrate, an isolation layer is formed on the substrate exposed by the fin, and the isolation layer covers a part of side walls of the fin; forming a dummy gate structure across the fin, including a dummy gate layer, where the dummy gate structure covers a part of the top and a part of the side walls of the fin; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, where the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate layer and forming an opening in the interlayer dielectric layer; removing partial thickness of the isolation layer exposed by the opening and forming a groove in the isolation layer; and forming a gate structure in the groove and the opening, where the gate structure crosses the fin and covers a part of the top and a part of the side wa

Abstract: A semiconductor structure and a method for forming same are provided, the method including: providing a base including a substrate and a fin protruding from the substrate, the substrate including a P-type logic region and a pull up transistor region; forming a gate layer across the fin; forming a mask spacer covering a side wall of a fin in the pull up transistor region and a side wall of a portion of a fin in the P-type logic region; removing a portion of thicknesses of the fins on both sides of the gate layer using the mask spacer as a mask, to form a groove enclosed by the fin and the mask spacer in the P-type logic region and a straight slot penetrating the fin and the mask spacer in the pull up transistor region along a direction perpendicular to the side wall of the fin; and forming a P-type source/drain doped layer in the groove and the straight slot.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a wafer having a functional region and a non-functional region surrounding the functional region; forming a first dielectric layer on the wafer; forming a first opening in the first dielectric layer in the non-functional region; and forming a first connection layer in the first opening. The first connection layer closes a top portion of the first opening, and a void is formed in the first connection layer in first opening.

Abstract: A semiconductor structure and a method for forming same are provided. In some implementations, a forming method includes: providing a base; forming a first electrode layer on the base; and forming a capacitor dielectric layer with a stacked structure on the first electrode layer and a second electrode layer on the capacitor dielectric layer, the capacitor dielectric layer including a bottom high-k dielectric layer, a leakage-proof dielectric layer, and a top high-k dielectric layer that are sequentially stacked from bottom to top, wherein the bottom high-k dielectric layer and the top high-k dielectric layer have a preset total deposition thickness, and wherein a proportion of a deposition thickness of the bottom high-k dielectric layer to the preset total deposition thickness is greater than a proportion of a deposition thickness of the top high-k dielectric layer to the preset total deposition thickness.

Abstract: A semiconductor structure and a method for forming same are provided.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first device region and a second device region; forming a first doped layer on the semiconductor substrate; forming a first fin layer on the first doped layer in the first device region; forming a second fin layer on the first doped layer in the second device region; forming a first isolation layer on the first doped layer in the first device region and covering sidewall surfaces of the first fin layer; forming a second isolation layer on the second doped layer in the second device region and covering portions of sidewall surfaces of the second fin layer and with a thickness smaller than a thickness of the first isolation layer; and forming a first gate structure on the first isolation layer and a second gate structure on the second isolation layer.

Abstract: An electrostatic discharge protection circuit and a semiconductor device are provided. The circuit includes: a power source terminal, a ground terminal, and a discharge path. The discharge path includes a clamp transistor and a MOS transistor connected in series and integrated into a same semiconductor substrate with different types. For the MOS transistor, a gate electrode is electrically connected to a substrate terminal; a first electrode is one of a source electrode and a drain electrode; a second electrode is another one of the source electrode and the drain electrode; the first electrode is electrically connected to a gate electrode of the clamp transistor; and the second electrode is electrically connected to the ground terminal. When an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor.