Abstract: A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hollow channel surrounded by the gate electrode and positioned between the source electrode and the drain electrode, a dielectric member positioned between the hollow channel and the gate electrode, a first insulating member positioned between the gate electrode and the source electrode, and a second insulating member positioned between the gate electrode and the drain electrode.

Abstract: A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage signal based on an input signal, and a drive signal control circuit configured to provide a drive signal connected to the switch circuit in response to the input signal. A voltage rising speed of the word line voltage signal is controlled by the drive signal.

Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.

Abstract: A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for receiving a reference voltage, and an enable terminal for receiving an enable signal of the duty cycle adjustment unit. The enable signal has a rising edge that is delayed relative to a rising edge of the output signal and a falling edge that is aligned with a falling edge of the output signal. The comparison unit compares a voltage level of the output signal with the reference voltage when the enable signal is in a stable voltage state and determine a bus condition in response to a comparison result.

Abstract: The present disclosure describes a chemical mechanical polishing device and a chemical mechanical polishing method. The chemical mechanical polishing device includes: a cleaning apparatus and a polishing pad conditioner disc positionally configurable relative to the cleaning apparatus, where the cleaning apparatus includes: a cleaning disc; a pre-polishing pad disposed inside the cleaning disc and configured to perform a pre-polishing operation of the polishing pad conditioner disc when positioned in contact with the polishing pad conditioner disc; a pre-polishing grinding liquid dispensing assembly disposed on a side edge of the cleaning disc and configured to supply a pre-polishing grinding liquid to the pre-polishing pad; and a rotation driver configured to drive the pre-polishing pad to rotate during the pre-polishing operation. The present disclosure beneficially reduces wafer scratches and increases evenness of distribution of a grinding liquid during polishing.

Abstract: The present disclosure discloses a resistive random access memory (RRAM) and a method for manufacture the RRAM. The method includes: providing a bottom interconnection layer; forming a bottom dielectric layer above the bottom interconnection layer, the bottom dielectric layer comprising a via through the bottom dielectric layer that exposes a portion of the bottom interconnection layer; and forming a bottom electrode layer in the via, the bottom electrode layer including a first electrode selectively grown above the bottom interconnection layer. The bottom electrode layer manufactured in such a way provides improved filling capability of the bottom electrode layer in the via.

Abstract: A method for fabricating a semiconductor structure includes providing a substrate, forming an interface layer on the substrate, and then performing a first annealing process on the interface layer under a nitrogen-containing environment to form a nitrogen-containing layer from a top portion of the interface layer. The first annealing process also deactivates non-bonded silicon ions and oxygen ions in the interface layer. The method further includes forming a high-k dielectric layer on the nitrogen-containing layer, and performing a second annealing process on the high-k dielectric layer to allow nitrogen ions in the nitrogen-containing layer to diffuse into the high-k dielectric layer to reduce a density of active oxygen vacancies in the high-k dielectric layer. Finally, the method includes forming a gate electrode layer on the high-k dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate having a core device and an IO device. The core device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The IO device includes a gate interface layer and a high-k dielectric layer on the gate interface layer. The gate interface layer of the core device and the gate interface layer of the IO device each are doped with fluoride ions.

Abstract: A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.

Abstract: In some embodiments, a semiconductor device and a fabricating method thereof are provided. The method can comprise: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming an epitaxial substrate layer on the semiconductor substrate on both sides of the gate structure; forming a hard mask layer conformally covering the epitaxial substrate layer, the gate structure and the semiconductor substrate; etching the hard mask layer to form a hard mask sidewall layer on sidewall surfaces of the gate structure and on the epitaxial substrate layer; using the hard mask sidewall layer as a mask to etch the epitaxial substrate layer and the semiconductor substrate to form trenches on both sides of the gate structure; and forming a stress layer in the trenches.

Abstract: A method for forming a semiconductor device includes providing a substrate structure having a plurality of semiconductor fins disposed on a substrate and a hard mask layer on the semiconductor fins. A first insulating material layer is formed covering the semiconductor fins, the hard masks, and the spaces between the semiconductor fins. Next, a first etch back process is performed to remove a top portion of the first insulating material layer to expose a portion of each of the semiconductor fins. Then dopants are implanted into remaining portions of the first insulating material layer and diffused into the semiconductor fins to form impurity regions. Next, a second etch back process is performed to remove a top portion of the remaining first insulating material layer to remove the implanted dopants in the first insulating material layer. Thereafter, a second insulating material layer is formed overlying the remaining first insulating material layer.

Abstract: A spiral inductor formed in a vertical plane relative to a planar surface of a substrate includes a plurality of through holes disposed in the vertical plane and spaced apart from each other, a metal interconnect structure on the top surface, and a redistribution layer on the bottom surface and having at least one bottom metal layer. The metal interconnect structure and the redistribution layer are connected to each other through the plurality of through holes to form the vertical spiral inductor. The thus formed vertical spiral inductor has a significantly reduced surface area comparing with lateral spiral inductors.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.

Abstract: A semiconductor device manufacturing method includes providing a wafer, which includes a semiconductor substrate, a semiconductor device located on the semiconductor substrate, an interlayer dielectric layer covering the semiconductor device, and a through hole penetrating through the interlayer dielectric layer and a portion of the semiconductor substrate. A metal layer is formed inside the through hole and on a surface of the interlayer dielectric layer. A first planarization process is conducted to remove a portion of the metal layer on the surface of the interlayer dielectric layer. The method also includes conducting an annealing alloy treatment and conducting a second planarization process to completely remove the metal layer on the surface of the interlayer dielectric layer. The manufacturing methods can slowly release stress of the wafer and effectively prevent cracks in silicon vias, thereby reducing TSV leakage problems, thus improving the reliability and yield of the devices.

Abstract: The present disclosure relates to a technical field of semiconductors and discloses a semiconductor resistor and a manufacturing method therefor.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. The current output circuit includes a first PMOS transistor and a second PMOS transistor. The impedance gain circuit includes a first end, a second end, a third end which is connected to a supply voltage, and a fourth end which is connected to the ground. A source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage.

Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.

Abstract: An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin. The second doped region includes a second portion of the substrate and a second region of the first fin. The device also includes a first gate structure on a portion of first and second regions of the first fin, a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration higher than the first doped region, and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration higher than the second doped region.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first source terminal formed of a material and connected to a first source, a first drain terminal formed of the material and connected to a first drain, a first gate overlapping a portion of the substrate that is between the first source and the first drain, and a first dielectric layer between the first gate and the substrate. The second transistor includes a control gate formed of the material and overlapping a part of the substrate that is positioned between a second source and a second drain, a second dielectric layer between the control gate and the substrate, a floating gate extending through the second dielectric layer to contact a doped region in the substrate, and an insulating member positioned between the control gate and the floating gate.