Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one first dummy gate in the first region and at least one second dummy gate in the second region. Further, the method includes forming a dielectric layer with a top surface leveling with a surface of the first dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench.

Abstract: Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer.

Abstract: The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer.

Abstract: A semiconductor device may include a first dielectric layer. The semiconductor device may further include a second dielectric layer overlapping the first dielectric layer and having a closed cavity structure. The semiconductor device may further include a first transistor disposed between the first dielectric layer and the closed cavity structure. The semiconductor device may further include a second transistor disposed between the first dielectric layer and the closed cavity structure. The semiconductor device may further include a trench isolation structure disposed between the first transistor and the second transistor and disposed between the first dielectric layer and the closed cavity structure.

Abstract: Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.

Abstract: A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface.

Abstract: A semiconductor device fabrication method is provided in which recesses are formed at source/drain positions in the substrate, removable sidewalls are formed on side walls of the recess, and the recesses then are etched to form Sigma shaped recesses. Selective epitaxial growth of substantially un-doped SiGe in the Sigma shaped recesses is performed, and the Sigma shaped recesses close to the surface of the substrate can be protected from epitaxial growth by the removable sidewalls. Epitaxial growth of SiGe doped with a P-type impurity can be performed in the Sigma shaped recesses after removing the sidewalls.

Abstract: A method for manufacturing a substrate may include processing a substrate material member to form a first remaining portion. The first remaining portion has a first cavity. A sidewall the first cavity is oriented at a first angle with respect to at least one of a horizontal plane and a bottom side of the first remaining portion. The method may further include providing a sacrificial material member in the first cavity. The method may further include processing the sacrificial material member when processing the first remaining portion to remove the sacrificial material member and to form a second remaining portion. The second remaining portion has a second cavity. A sidewall the second cavity is oriented at a second angle with respect to at least one of the horizontal plane and a bottom side of the second remaining portion. The second angle is smaller than the first angle.

Abstract: A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

Abstract: A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element.

Abstract: MEMS devices and methods for forming the same are provided. A first metal interconnect structure is formed on a first semiconductor substrate to connect to a CMOS control circuit in the first semiconductor substrate. A bonding layer having a cavity is formed on the first metal interconnect structure, and then bonded with a second semiconductor substrate. A conductive plug passes through a first region of the second semiconductor substrate, through the bonding layer, and on the first metal interconnect structure. A second metal interconnect structure includes a first end formed on the first region of the second semiconductor substrate, and a second end connected to the conductive plug. Through-holes are disposed through a second region of the second semiconductor substrate and through a top portion of the bonded layer that is on the cavity to leave a movable electrode to form the MEMS device.

Abstract: An image sensor device includes a top substrate and a subassembly. The top substrate includes a plurality of connection pillars, and the subassembly includes a plurality of connection pads. The connection pillars on the top substrate are bonded to the connection pads in the subassembly. The connection pillars are formed of a first metal and the connection pads are formed of a second metal.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of trenches in a semiconductor substrate, on opposite sides of a gate electrode of a P-type metal-oxide-semiconductor (PMOS) disposed on the semiconductor substrate. The method further includes forming an embedded silicon germanium layer inside the trenches, and forming a capping layer on the embedded silicon germanium layer, wherein the embedded silicon germanium layer and the capping layer are doped with boron (B).

Abstract: A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the semiconductor substrate. The method also includes forming dummy gates formed over side and top surfaces of the fins; forming a precursor material layer with a surface higher than top surfaces of the fins to cover the dummy gates and the semiconductor substrate; performing a thermal annealing process to convert the precursor material layer into a dielectric layer having a plurality of voids; and planarizing the dielectric layer to expose the top surfaces of the dummy gates. Further, the method also includes performing a post-treatment process using oxygen-contained de-ionized water on the planarized dielectric layer to eliminate the plurality of voids formed in the dielectric layer; removing the dummy gates to form trenches; and forming a high-K metal gate structure in each of the trenches.

Abstract: The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction.

Abstract: A method for manufacturing one or more semiconductor devices may include the following steps: providing a dielectric layer on a substrate structure that includes a first electrode and a second electrode; providing a first mask on the dielectric layer; providing a second mask, which overlaps the first mask and has a designated structure, wherein a portion of the first mask is positioned between a first portion and a second portion of the designated structure in a layout view of a process structure that includes the first mask and the second mask; and performing a removal process through the first portion of the designated structure and through the second portion of the designated structure to form a first contact hole and a second contact hole in a remaining portion of the dielectric layer, wherein the two contact holes expose the two electrodes, respectively.

Abstract: A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures.

Abstract: A method of selectively etching a semiconductor device and manufacturing a BSI image sensor device includes etching a doped silicon substrate with an HNA solution for a predetermined time duration to obtain an etching solution having a concentration C1 of nitrite ions, etching the semiconductor device using the obtained etching solution. Etching the semiconductor device requires an initial concentration C0 of nitride ions that is lower than C1. The HNA solution comprises a hydrofluoric acid (HF), a nitric acid (HNO3), and a acetic acid (CH3COOH). The BSI image sensor device will have a uniform thickness when etched using the thus obtained etching solution.

Abstract: Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.