Abstract: A semiconductor integrated circuit device comprising a semiconductor substrate, e.g., silicon wafer, silicon on insulator. The device has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. The device also has a channel region within a portion of the semiconductor substrate within a vicinity of the gate structure and a lightly doped source/drain regions in the semiconductor substrate to from diffused pocket regions underlying portions of the gate structure. The device has sidewall spacers on edges of the gate structure. The device also has an etched source region and an etched drain region. Each of the first source region and the first drain region is characterized by a recessed region having substantially vertical walls, a bottom region, and rounded corner regions connecting the vertical walls to the bottom region.

Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.

Abstract: The present invention provides a multi-die semiconductor package structure and a manufacturing method thereof, which includes providing at least two dies and a lead frame including a die pad and a lead wire located at the periphery of the die pad, the die pad has a via hole at the edge thereof, binding a base opposite side of a first die to the die pad; electrically connecting the first die to the lead wire through the via hole; binding a base side of a second die to the die pad, the first and second dies are disposed on the opposite sides of the die pad respectively; electrically connecting the second die to the lead wire; stacking other dies above the first or second die and electrically connecting them to the lead wire; and encapsulating said at least two dies and the lead frame to form a package.

Abstract: A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires connected with the leads. By means of the above-described lead frame, the subsequent packaging process of the semiconductor chip; including dual chips and/or multi-chips assembly, is simplified and the effect of the manufacturing process is improved, at the same time, the manufacturing cost is reduced.

Abstract: A failure alarm device includes: an operation instruction capturing unit; an operation status signal capturing unit; and a timing and alarming unit for starting timing when the operation instruction capturing unit captures a start-operation instruction and the operation status signal capturing unit captures an operation status signal indicative of that the CMP apparatus is in the preset operation status, and for alarming if a duration of the operation status signal indicative times out. During operation of the CMP apparatus, when there occurs an unexpected failure in a computer or control software or the CMP apparatus is powered off, an alarm can be initiated in a timely way so as to inform an apparatus engineer to obviate the failure, and wafer rejects in the CMP apparatus can be avoided. A failure alarm method is also provided.

Abstract: A method for forming a capacitor structure for a dynamic random access memory device. The method includes forming a device layer overlying a semiconductor substrate, e.g., silicon wafer. The method includes forming a first interlayer dielectric overlying the device layer and forming a via structure within the first interlayer dielectric layer. The method includes forming a first oxide layer overlying the first interlayer dielectric layer and forming a stop layer overlying the first oxide layer. The method includes forming a second oxide layer overlying the first stop layer and forming a trench region through a portion of the second oxide layer, through a portion of the stop layer, and a portion of the second oxide layer. A bottom electrode structure is formed to line the trench region. The bottom electrode structure includes an inner region. The bottom electrode structure is coupled to the via structure.

Abstract: The present invention provides a method for decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensures programming memory cell normally; selecting two parameters from the initial programming condition as variables for a program disturb test; performing the program disturb test to the memory cell for at least two combined values of the variables; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb in memory cells and can be performed easily.

Abstract: A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures. Each of the chips has conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures. The method then applies a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass. A step of cleaning the exposed portion of silicon nitride using an isotropic component is also included.

Abstract: The present invention discloses a PCI Express interface and a method of signal processing, and particularly relates to the physical coding sub-layer that transmits data between physical media access layer and media access control layer of the PCI Express. The PCI express interface of present invention enables physical coding sub-layer to be able to receive or output 8-bit data as well as to receive or output 16-bit data by adding an input interface unit and an output interface unit in physical coding sub-layer, thereby the data formats of physical coding sub-layer and media access control layer are compatible; enables the physical coding sub-layer to be able to handle data with sampling errors during transmission from physical media access layer to physical coding sub-layer by adding data adjustment unit in the physical coding sub-layer and applying corresponding signal processing method, thereby it ensures the integrity of the data transmitted over physical coding sub-layer.

Abstract: The present invention provides a method of decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensure programming memory cell normally; selecting one parameter from the initial programming condition as a variable for the program disturb test; performing the program disturb test to the memory cell for at least two values of the variable; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb for the memory cell and can be performed easily.

Abstract: A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate including a core device region and an input/output device region, each of which is formed with a gate dielectric layer and a gate on the gate dielectric layer; performing a first ion implantation in the core device region and the input/output device region of the semiconductor substrate with the gate as a mask; performing a rapid thermal annealing to form low-doped source/drain regions in the semiconductor substrate at both sides of the gate dielectric layers of the core device region and the input/output device region; forming spacers over the sidewalls of the gate dielectric layers and gates of the core device region and the input/output device region; and performing a third ion implantation in the core device region and the input/output device region of the semiconductor substrate with the gate and spacer as a mask to form a heavily doped source/drain region.

Abstract: A method and apparatus for the decapsulation of integrated circuit packages. The apparatus includes a support member, the support member having an open region and an adjustable device coupled to the support member. The adjustable device can be adapted to hold a BGA package such that a surface region of the BGA package is spatially disposed to face a decapsulation source and a plurality of balls on the BGA package remain free from contact from the decapsulation source and free from contact from a thermal source capable of causing damage to one or more of the balls. The decapsulation source is provided to subject a portion of the surface region of the BGA package for removal of the portion of the BGA package.

Abstract: The invention discloses a method for fabricating an embedded semiconductor memory device, comprising: preparing a semiconductor substrate comprising a region IA and a region IB; forming gate dielectric layers and gate structures sequentially on the semiconductor substrate, with the gate dielectric layer in region IA being a charge trap region, and the gate dielectric layer in region IB being a non-charge trap region; forming source/drain extension regions in region IA and region IB of the semiconductor substrate; and forming source/drain regions in region IA and region IB of the semiconductor substrate. There is provided correspondingly an embedded semiconductor memory device. The invention also provides an embedded semiconductor memory device and a method for fabricating the same. A two-bit storage operation can be enabled for the embedded semiconductor memory device according to the invention so as to achieve high-density storage.

Abstract: A method for fabricating semiconductor wafers using physical vapor deposition. The method includes maintaining a substrate on a susceptor in a chamber. The substrate has a face positioned within a vicinity of a target material, which is within the chamber. The target member comprises a first side and a second side. Preferably, the first side is positioned toward the face of the substrate. The method includes operating a magnet device fixed about a rotating member, which is coupled to the chamber and is coupled to a drive motor, which is coupled to a driver. A magnet device is positioned from a center region of the rotating member by a predetermined dimension. The method includes moving the magnet device in an annular manner about the center region using the rotating member. The magnet device is rotated at a velocity v and influences a spatial region, which is positioned overlying the second side of the target.

Abstract: The present invention provides a method for fabricating a pixel cell of CMOS image sensor, comprising: preparing a semiconductor substrate divided into region I and region II; forming an insulation layer on the surface of the semiconductor substrate in the region I and a gate dielectric layer on the surface of the semiconductor substrate in the region II; forming a poly-silicon gate on the surface of the semiconductor substrate in the region II; forming a deep doped well in the region I through an ion implantation with high energy; performing an ion implantation with low energy in the region I and an ion implantation for lightly doped source/drain in the region II simultaneously; and forming source/drain regions in the semiconductor substrate in the region II.

Abstract: System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.

Abstract: A method for manufacturing semiconductor substrates. The method includes providing a semiconductor wafer, which has an upper surface, a backside surface, and an edge region around a periphery of the semiconductor wafer. In a preferred embodiment, the upper surface is often for the manufacture of the integrated circuit device elements themselves. The method includes subjecting the semiconductor wafer to one or more process steps to form one or more films of materials on the backside surface. The method mounts the semiconductor wafer to expose the backside surface. The method rotates the semiconductor wafer in a circular manner. In a specific embodiment, the method includes supplying an acid solution containing fluorine bearing species, a nitric acid species, a surfactant species, and an organic acid species, on at least the backside surface as the semiconductor wafer rotates.

Abstract: A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the surface region and forms an interconnect layer overlying the first interlayer dielectric layer. The method also forms a low K dielectric layer overlying the interconnect layer, which has a predetermined shape. The method forms a copper interconnect layer overlying the low K dielectric layer. In a preferred embodiment, the low K dielectric layer maintains the predetermined shape using a dummy pattern structure provided within a portion of the low K dielectric layer to mechanically support and maintain the predetermined shape of the low K dielectric layer between the interconnect layer and the copper interconnect layer.

Abstract: A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.