Abstract: The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal blocks made of a second metal material. The plurality of first metal blocks are used to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.

Abstract: The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.

Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

Abstract: In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.

Abstract: The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. The method further includes attaching the growth substrate to a bonding substrate such that the second dielectric layer attaches to the bonding substrate; removing the sacrificial substrate; and removing the buffer layer so as to expose the graphene layer.

Abstract: A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member.

Abstract: A fin-type bipolar semiconductor device includes a base region having a first portion in a semiconductor substrate and a first semiconductor fin on the adjacent first portion, a collector region having a second portion in the semiconductor substrate and a second semiconductor fin on the adjacent second portion, and an emitter region having a third region in the semiconductor substrate and a third semiconductor fin on the adjacent third portion. The second portion is adjacent the first portion, and the third portion is adjacent the first portion and forms an emitter junction in the semiconductor substrate. The second portion is not adjacent to the third portion. The first, second, and third semiconductor fins are physically separated from each other. The fin-type bipolar device exhibits low leakage current, good linearity and uniformity of electrical characteristics to facilitate device matching.

Abstract: Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device.

Abstract: The present disclosure relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer to cover the gate lines; planarizing the second dielectric layer; forming an insulating buffer material layer; patterning the insulating buffer material layer to form a patterned insulating buffer layer containing multiple separate portions, each separate portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer.

Abstract: The present disclosure provides fin field-effect transistors and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a first region and a second region; forming first fins in the first region and second fins in the second region; forming a liner oxide layer on side surfaces of the first fins, the second fins and a surface of the substrate; forming an insulating barrier layer on the liner oxide layer in the first region; forming a precursor material layer on the insulating barrier layer in the first region and on the liner oxide layer in the second region; performing a curing annealing process to convert the precursor material into an insulation layer; and removing a top portion of the insulation layer to form an isolating layer and removing portions of the liner oxide layer, the insulating barrier layer, the first oxide layer and the second oxide layer.

Abstract: A nonvolatile memory includes a first array bank coupled to a first bit-line, a second array bank coupled to a second bit-line, a pre-charging circuit, a first selection circuit, a second selection circuit, and a sense amplifier. An address enable signal sent to the first selection circuit controls whether the pre-charging circuit needs to pre-charge the first bit-line and the second bit-line. The sense amplifier is configured to compare a first voltage from the first output terminal of the pre-charging circuit with a second voltage from the second output terminal of the pre-charging circuit to obtain a result indicating data information stored in the first array bank or in the second array bank. The second selection circuit is configured to connect a reference current to the first input terminal or the second input terminal of the sense amplifier based on a first word-line signal and a second word-line signal.

Abstract: Wafer bonding methods and wafer bonding structures are provided. An exemplary wafer bonding method includes providing a first wafer; forming a first interlayer dielectric layer and a first bonding layer passing through the first interlayer dielectric layer on the surface of the first wafer; providing a second wafer; forming a second interlayer dielectric layer and a second bonding layer passing through the second interlayer dielectric layer on surface of the second wafer; forming a self-assembling layer on at least one of a surface of the first interlayer dielectric layer and a surface of the second interlayer dielectric layer; and bonding the first wafer with the second wafer, the first bonding layer and the second bonding layer being fixed with each other, and the first interlayer dielectric layer and the second interlayer dielectric layer being fixed with each other by the self-assembling molecular layer.

Abstract: A power-on-reset circuit includes an execution circuit and a control circuit. The execution circuit includes a first input terminal connected to a power supply, a second input terminal and the first output terminal each initially are at a low level. The first output terminal transitions from the low level to a high level when the first input terminal and the second input terminal have a voltage not less than a predetermined voltage. The control circuit includes a third input terminal connected to the first output terminal, a fourth input terminal connected to the first input terminal, and a second output terminal connected to the second input terminal. The second input terminal transitions from the low level to the high level when a difference between the voltage at the first input terminal and the voltage at the first output terminal is greater than the predetermined voltage.

Abstract: A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: forming a dielectric layer on a semiconductor substrate; forming a functional layer on the dielectric layer; forming a hard mask layer on the functional layer; patterning the semiconductor substrate to form an opening on the semiconductor substrate, wherein the opening goes through the hard mask layer, the functional layer and extends into the dielectric layer; performing an oxidization process on side surfaces of the functional layer inside the opening to form oxide layers; performing a first process on the semiconductor substrate to remove a portion of the dielectric layer underneath the opening to expose the semiconductor substrate; and removing the oxide layers on the side surfaces of the functional layer to form a contact hole. The contact hole has a wider opening in the upper part than in the lower part.

Abstract: A method for forming a MEMS device is provided. The method includes providing a first wafer and a second wafer. The first wafer has a trench on a top surface of the first wafer and a fixed electrode on the bottom of the trench, and the second wafer has a polishing stop layer, a sacrificial layer, and a movable electrode. The method also includes bonding the first wafer and the second wafer with the top surface of the first wafer facing the top surface of the second wafer and the movable electrode on the second wafer located above the trench on the first wafer; removing the second wafer by polishing the second wafer from a backside of the second wafer until reaching the polishing stop layer; and releasing the movable electrode by removing a portion of the polishing stop layer and the sacrificial layer to form the MEMS device.

Abstract: A photoresist coating apparatus is provided. The photoresist coating apparatus includes a base; and a position platform moving back and forth along a scanning direction on the base. The photoresist coating apparatus also includes an imprinter having a trench configured to hold photoresist and fixed on the position platform; and a photoresist spray nozzle disposed above the imprinter and configured to spray the photoresist into the trench. Further, the photoresist coating apparatus includes a reticle frame configured to install a cylindrical reticle and enable the cylindrical reticle to rotate around a center axis and contact with the imprinter so as to coat the photoresist in the trench on a surface of the cylindrical reticle.

Abstract: A semiconductor device includes a silicon substrate, a silicon germanium (SiGe) layer including a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion, a first dielectric layer disposed over a side surface of the fin structure and a top surface of the lower portion of the silicon germanium (SiGe) layer, an indium gallium arsenide (InGaAs) layer disposed over a surface of the first dielectric layer, a high k oxide layer disposed over a surface of the InGaAs layer, and a metal layer disposed over a surface of the high k oxide layer. The InGaAs layer includes a source region, a channel region, and a drain region. The metal layer is configured to be a first gate electrode, and the fin structure in the SiGe layer is configured to be a second gate electrode.