Abstract: A method of forming a sealing structure for a bonded wafer is provided. The method includes providing the lower wafer and the upper wafer, forming a sealing material layer on each of the lower wafer and the upper wafer, forming a mask layer on the sealing material layer on each of the lower wafer and the upper wafer, etching the sealing material layer using the mask layer as an etch mask, so as to form a first protrusion at an edge of the lower wafer and a second protrusion at an edge of the upper wafer, and bonding the first protrusion and the second protrusion together to form the sealing structure. The sealing structure encloses a gap between the lower wafer and the upper wafer at an edge of the bonded wafer, so as to form a hermetically sealed cavity at the edge of the bonded wafer.

Abstract: The present disclosure provides apparatus and methods for overlay measurement. An exemplary overlay measurement apparatus includes an illuminating unit configured to generate illuminating light to illuminate a first overlay marker formed on a wafer to generate reflected light; and a first measuring unit configured to receive the reflected light from the first overlay marker to cause the reflected light to laterally shift and shear to generate interference light, to receive the interference light to form a first image, and to determine existence of an overlay offset and an exact value of the overlay offset, according to the first image.

Abstract: A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth inverters, a third power supply supplying power to the second transfer gate, first and second signals having opposite logic levels for controlling the first transfer gate. The third power supply is significantly lower than the first or second power supply. The leakage current of the receiver is significantly reduced in the core when the second power supply remains on but the first power supply is turned off while the performance of the receiver remains the same.

Abstract: A semiconductor device includes a plurality of substantially vertical semiconductor pillars on a substrate, and a hard mask layer overlying the plurality of semiconductor pillars. A contiguous portion of the hard mask layer connects two or more of the plurality of semiconductor pillars.

Abstract: A write tracking circuit includes a dummy memory cell coupled to a first dummy bit line, a second dummy bit line, and a dummy word line, a logic operation unit coupled to the dummy word line and to the first dummy bit line and configured to output a write feedback signal based on a logic operation of a signal on the dummy word line and a signal on the first dummy bit line, and a delay unit coupled to the dummy memory cell at a storage node. The write tracking circuit provides a correct feedback signal to the clock generation module to ensure normal operation of the peripheral circuit, when a data write operation to the dummy memory cell failed.

Abstract: The disclosed subject matter provides a Fin-FET with a thinned-down InP layer and thinning-down method thereof. In a Fin-FET, the fin structure is made of InGaAs and an InP layer is formed to cover the fin structure. The InP layer is obtained from an initial InP layer formed on the fin structure through a thinning down process including converting a surface portion of the InP layer into a Phosphorus-rich layer and removing the Phosphorus-rich layer. The thickness of the ultimately-formed InP layer is less than or equal to 1 nm. According to the disclosed method, the InP layer in the Fin-FET may be easily thinned down, and during the thinning-down process, contamination may be avoided.

Abstract: A method is provided for fabricating a photolithographic mask. The method includes providing a transparent substrate; and forming an opaque layer on the transparent substrate. The method also includes writing layout patterns with at least one sub-resolution assistant feature with non-uniform size along a longitudinal direction to increase an adhesion force between the sub-resolution assistant feature with non-uniform size along the longitudinal direction and the transparent substrate in the opaque layer. Further, the method include cleaning residual matters generated by writing the layout patterns in the opaque layer. Further, the method also includes spin-drying the transparent substrate with the layout patterns and the sub-resolution assistant feature with non-uniform size along the longitudinal direction.

Abstract: The present disclosure provides Efuse bit cells and read/write methods thereof, and Efuse arrays. An exemplary Efuse bit cell includes a data latch configured to latch data of the Efuse bit cell, having two branches with a fuse disposed in a first branch and a resistor disposed in a second branch; a selection controller configured to control connections between one terminal of the first branch and a power source and between one terminal of the second branch and the power source, another terminal of the first branch and another terminal of the second branch being connected to ground; a first diode and a second diode, one of the first diode and the second diode being configured to input a write data signal; and a pass unit configured to transmit data stored in the Efuse bit cell and output a bit line signal.

Abstract: A method for forming a semiconductor device includes forming a buried doped layer in a semiconductor substrate and forming a plurality of first trenches that expose the buried doped layer. A first dielectric layer is formed covering sidewalls of the first trenches, and a doped polysilicon layer is formed covering side surfaces of the first dielectric layer and bottom portions of the first trenches. The method also includes forming a second trench in each of the plurality of first trenches, and each second trench extending through a bottom portion of the doped polysilicon layer and the buried doped layer into a lower portion of the substrate. The method also includes forming a second dielectric layer inside each second trench. An isolation pocket structure is formed that includes the doped buried layer at the bottom and sidewalls that includes the doped polysilicon layer sandwiched between the first and second dielectric layers.

Abstract: A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination.

Abstract: A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

Abstract: An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor, and a first resistor connected in series with the capacitor between the power and ground supplies. The ESD clamp circuit also includes a clamp transistor having a first terminal connected to the power supply and a second terminal connected to the ground terminal, an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to the gate of the clamp transistor, a feedback transistor connected across the inverter, and a second resistor having a first terminal connected to the gate of the clamp transistor and to a second terminal to the ground supply.

Abstract: A semiconductor device may include a gate electrode, an insulating layer, a first channel member, and a second channel member. The insulating layer may overlap the gate electrode. The first channel member may be positioned between the gate electrode and the insulating layer. The second channel member may be positioned between the gate electrode and the first channel member. A semiconductor material of the second channel member may be different from a semiconductor material of the first channel member.

Abstract: A microelectromechanical system (MEMS) acceleration sensor includes a mass bar, a first spring disposed on a first set of opposite sides of the mass bar and configured to secure the mass bar in a first direction, an interdigital structure disposed along a second set of opposite sides of the mass bar in a second direction perpendicular to the first direction, a detection electrode corresponding to the interdigital structure, and a second spring disposed on the second set of opposite sides and configured to secure the mass bar in the second direction. The first spring has a frame shape, and the second spring has an S-shape. Through the second spring, the acceleration sensor is less sensitive to acceleration on the other direction, so that the detection performance of the acceleration sensor is improved.

Abstract: A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series connected between the word line and a reset line. A set path is formed through the first diode and the random access memory cell element, and a reset path is formed through the random access memory cell element and the second diode. The first diode is configured to performed a read operation and a set operation. The second diode is configured to perform a reset operation. The memory cell has higher forward current, lower leakage current and smaller size comparing with conventional memory cells.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the first conductor; preparing a second substrate; providing a third conductor, which is configured to electrically connect two elements associated with the second substrate; providing a fourth conductor on the second substrate, wherein the fourth conductor is electrically connected to the third conductor; providing a fifth conductor on the fourth conductor; and combining the fifth conductor with the second conductor through eutectic bonding.

Abstract: A method for testing an equipment automation program may be implemented using a hardware device and may include the following steps: receiving user input through a user interface of the device; automatically identifying a test scenario based on the user input; automatically and sequentially fetching a plurality of messages according to the test scenario; and automatically and sequentially sending the messages to the equipment automation program.

Abstract: The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

Abstract: The present application provides a flash memory device. The flash memory device includes a semiconductor substrate; and a plurality of tunnel oxide layers formed on a surface of the semiconductor substrate. The flash memory device also includes a floating gate having a first portion with a width smaller than a width of the tunnel oxide layer and a second portion with a width greater than the width of the first portion formed on the first portion formed on each of the floating silicon oxide layers. Further, the flash memory device includes a plurality of shallow trench isolation structures formed in the surface of the semiconductor substrate between adjacent floating gates and the tunnel oxide layers; and liner oxide layers formed on side surfaces of the first portion of the floating gates.