Abstract: A semiconductor structure and a forming method thereof are provided. The semiconductor structure includes: a substrate, including a device cell area and an isolated area located on a periphery of the device cell area; an isolation structure, located in the substrate of the isolated area; a device gate structure, located on the substrate of the device cell area; and a source/drain doped layer, embedded into the substrate of the device cell area on two sides of the device gate structure, the source/drain doped layer including a source/drain bulk layer, a side wall of the source/drain bulk layer located on an edge of the device cell area and the isolation structure being spaced apart.

Abstract: A semiconductor structure and a method for forming the same are provided. The forming method includes: forming discrete poly gate layers on a base of a first region and a second region, the poly gate layer of the first region including a bottom gate layer and a top gate layer protruding out of the bottom gate layer, the top gate layer and the bottom gate layer defining a groove, and a polish block layer being formed on the sidewall of the groove; forming an interlayer dielectric layer on the base on the side of the poly gate layer; removing the poly gate layer of the second region to form a gate opening; and forming a metal gate layer in the gate opening.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: Semiconductor structures and methods for forming same are disclosed. In one form, a structure includes: a base, including a first device region and a second device region, where the first device region includes a channel region, and preset regions located on two sides of the channel region, and a well pick-up region surrounding the channel region and the preset regions; a first isolation structure, located in the base between the preset regions and the well pick-up region and between the well pick-up region and the adjacent second device region; a poly gate, covering the channel region; a first source/drain doping region, located in the preset regions on two sides of the poly gate; a metal gate, located on the base in the second device region; a support structure, located on the top of the first isolation structure; and an interlayer dielectric layer, covering side walls of the poly gate, the metal gate, and the support structure.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.