Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

Abstract: A method includes providing a substrate; forming a bottom layer over the substrate; forming a middle layer over the bottom layer, a top surface of which including a photosensitive moiety having a first end anchored in the middle layer and a second end extending away from the top surface of the middle layer; forming a photoresist layer over the middle layer; exposing the photoresist layer to a radiation source; and developing the photoresist layer to form a pattern. The photosensitive moiety, which includes one of a photo-acid generator (PAG), a photo-base generator (PBG), photo-decomposable base (PDB), or photo-decomposable quencher (PDQ), may be anchored to a polymer backbone forming the middle layer via one or more linker groups. A distance by which the photosensitive moiety extends into the photoresist layer may be determined by a length of the linker group.

Abstract: A semiconductor device includes a source region and a drain region laterally spaced from each other and overlying a substrate, a metal oxide semiconductor channel layer overlying, and contacting, the source region and the drain region, a first gate dielectric layer overlying a portion of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a portion of the metal oxide semiconductor channel layer, a second gate dielectric layer contacting a sidewall of the metal oxide semiconductor channel layer, and a second gate electrode contacting a sidewall of the second gate dielectric layer and spaced from the metal oxide semiconductor channel layer by the second gate dielectric layer. The first gate electrode may be a floating gate that stores electrical charges, and turns on or off a first transistor including the source region and the drain region.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a plurality of memory cells arranged in a cell array over the substrate. Each of the memory cells includes a latch circuit, a pass-gate transistor, and an isolation transistor. The latch circuit is formed by two cross-coupled inverters. The pass-gate transistor is coupled between an output terminal of the latch circuit and a bit line. The isolation transistor includes a drain and a gate, both coupled to the output terminal of the latch circuit, and a source that is floating. A first gate length of the isolation transistor is greater than a second gate length of the pass-gate transistor and a plurality of transistors within the latch circuit.

Abstract: A fabrication method for a semiconductor structure is provided. The method includes: forming a base substrate; forming gate structures on the base substrate where each gate structure includes a first gate portion with first doping ions on the base substrate and a second gate portion on the first gate portion; forming a metal layer on the second gate portions; and forming a metal silicide layer by reacting a portion of the metal layer with each second gate portion through an annealing process. When forming the metal silicide layers, a reaction between the metal layer and the second gate portions has a first reacting rate and a reaction between the metal layer and the first gate portions has a second reacting rate; and the second reacting rate is smaller than the first reacting rate.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

Abstract: A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.

Abstract: A device is disclosed that includes a memory bit cell coupled to a bit line, a word line, a pair of metal islands and a pair of connection metal lines. The word line is electrically coupled to the memory bit cell and is elongated in a first direction. The pair of metal islands are disposed at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are elongated in a second direction, and are configured to electrically couple the pair of metal islands to the memory bit cell, respectively. The pair of connection metal lines are separated from the bit line in a layout view. A method of fabricating the device is also provided.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a wiring layer having a metal line, and forming a patterned disposable material layer over the wiring layer and having an opening aligned with the metal line. The method also includes depositing a first dielectric film in the opening and in contact with the metal line, and removing the patterned disposable material layer to leave the first dielectric film. The method further includes depositing a second dielectric film over the first dielectric film, and etching the second dielectric film to form a trench above the first dielectric film. In addition, the method includes removing a portion of the first dielectric film to form a via hole under the trench, and depositing a conductive material in the trench and the via hole.

Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor.

Abstract: A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.